A4984SLPTR-T View Datasheet(PDF) - Allegro MicroSystems

Part Name

Description

MFG CO.

A4984SLPTR-T

DMOS Microstepping Driver with Translator And Overcurrent Protection

Allegro MicroSystems 

Prev 11 12 13 14 15 16 17 18 19 20 Next

A4984

DMOS Microstepping Driver with Translator

And Overcurrent Protection

ES Package, 24-Pin QFN with Exposed Thermal Pad

4.00 ±0.15

24

1

2

A

4.00 ±0.15

25X D

0.08 C

0.25

+0.05

–0.07

0.50 BSC

C

SEATING

PLANE

0.75 ±0.05

0.45 MAX

2

1

B

2.70

24

2.70

24

0.95

1

2

0.30

0.50

2.70 4.10

2.70

4.10

C PCB Layout Reference View

For Reference Only; not for tooling use (reference JEDEC MO-220WGGD)

Dimensions in millimeters

Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area

B Exposed thermal pad (reference only, terminal #1

identifier appearance at supplier discretion)

C Reference land pattern layout (reference IPC7351

QFN50P400X400X80-25W6M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances; when

mounting on a multilayer PCB, thermal vias at the exposed thermal pad land

can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

D Coplanarity includes exposed thermal pad and terminals

Allegro MicroSystems, Inc.

19

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Share Link: