A4985SLPTR-T View Datasheet(PDF) - Allegro MicroSystems

Part Name

Description

MFG CO.

A4985SLPTR-T

DMOS Microstepping Driver with Translator And Overcurrent Protection

Allegro MicroSystems 

Prev 21 22

A4985

DMOS Microstepping Driver with Translator

And Overcurrent Protection

LP Package, 24-Pin TSSOP with Exposed Thermal Pad

7.80 ±0.10

24

A

12

24X

0.10 C

0.25

+0.05

–0.06

B

4.32±0.05

0.65

3.00±0.05 4.40 ±0.10 6.40 ±0.20

4° ±4

0.15

+0.05

–0.06

0.60 ±0.15

(1.00)

0.65

0.45

3.00

6.10

C

SEATING

PLANE

1.20 MAX

0.15 MAX

0.25

SEATING PLANE

GAUGE PLANE

1.65

4.32

C PCB Layout Reference View

For reference only

(reference JEDEC MO-153 ADT)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area

B Exposed thermal pad (bottom surface)

C Reference land pattern layout (reference IPC7351

TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a multilayer

PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

Allegro MicroSystems, Inc.

21

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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