Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

A4987SLPTR-T View Datasheet(PDF) - Allegro MicroSystems

Part Name
Description
MFG CO.
'A4987SLPTR-T' PDF : 16 Pages View PDF
Prev 11 12 13 14 15 16
A4987
DMOS Dual Full-Bridge PWM Motor Driver
with Overcurrent Protection
ES Package
Pin-out Diagrams
LP Package
OUT2B 1
PH2 2
GND 3
CP1 4
CP2 5
VCP 6
PAD
18 OUT1B
17 PH1
16 GND
15 REF
14 IN01
13 VDD
CP1 1
CP2 2
VCP 3
VREG 4
IN02 5
IN12 6
IN11 7
ROSC 8
SLEEP 9
VDD 10
IN01 11
REF 12
PAD
24 GND
23 PH2
22 OUT2B
21 VBB2
20 SENSE2
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
15 OUT1B
14 PH1
13 GND
Terminal List Table
Name
Number
ES
LP
Description
CP1
4
1
Charge pump capacitor terminal
CP2
5
2
Charge pump capacitor terminal
PH1
17
14
Logic input
PH2
2
23
Logic input
GND
3, 16
13, 24 Ground*
IN02
8
5
Logic input
IN12
9
6
Logic input
NC
No connection
OUT1A
21
18
DMOS Full Bridge 1 Output A
OUT1B
18
15
DMOS Full Bridge 1 Output B
OUT2A
22
19
DMOS Full Bridge 2 Output A
OUT2B
1
22
DMOS Full Bridge 2 Output B
REF
IN11
15
12
Gm reference voltage input
10
7
Logic input
ROSC
11
8
Timing set
SENSE1
20
17
Sense resistor terminal for Bridge 1
SENSE2
23
¯S¯ ¯L¯ ¯E¯ ¯E¯ ¯P¯
12
20
Sense resistor terminal for Bridge 2
9
Logic input
IN01
14
11
Logic input
VBB1
19
16
Load supply
VBB2
24
21
Load supply
VCP
6
3
Reservoir capacitor terminal
VDD
13
10
Logic supply
VREG
7
4
Regulator decoupling terminal
PAD
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
Allegro MicroSystems, Inc.
14
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]