A67L0618E-3.2 View Datasheet(PDF) - AMIC Technology
Part Name
Description
MFG CO.
'A67L0618E-3.2' PDF : 18 Pages View PDF
A67L0618/A67L9336
AC Characteristics (Note 4)
(0°C ≤ TA ≤ 70°C, VCC = +3.3V± 5%)
Symbol
Clock
Parameter
-2.6
-2.8
-3.2
-3.5
-3.8
-4.2
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max
tKHKH
Clock cycle time
tKF
Clock frequency
tKHKL
Clock HIGH time
tKLKH
Clock LOW time
Output Times
4.0 - 4.4 - 5.0 - 6.0 - 6.7 - 7.5 -
ns
- 250 - 227 - 200 - 166 - 150 - 133 MH
1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 -
ns
1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 -
ns
tKHQV Clock to output valid
- 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns
tKHQX Clock to output invalid
1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 -
ns
tKHQX1 Clock to output in Low-Z 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 -
ns 1,2,3
tKHQZ Clock to output in High-Z 1.5 2.6 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.5 ns 1,2,3
tGLQV
OE to output valid
- 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns
4
tGLQX
OE to output in Low-Z
0
-
0
-
0
-
0
-
0
-
0
-
ns 1,2,3
tGHQZ
OE to output in High-Z
- 2.6 - 2.8 - 3.0 - 3.0 - 3.0 - 3.5 ns 1,2,3
Setup Times
tAVKH
Address
tEVKH
Clock enable ( CEN)
tCVKH
Control signals
tDVKH
Data-in
Hold Times
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 -
ns
5
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 -
ns
5
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 -
ns
5
1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 -
ns
5
tKHAX
tKHEX
tKHCX
tKHDX
Address
Clock enable ( CEN)
Control signals
Data-in
0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 -
ns
5
0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 -
ns
5
0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 -
ns
5
0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 -
ns
5
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured ±200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of
CLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK (when ADV/LD is LOW) to remain enabled.
PRELIMINARY (March, 2006, Version 0.1)
12
AMIC Technology, Corp.
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