A67P83181E-10.0F View Datasheet(PDF) - AMIC Technology
Part Name
Description
MFG CO.
'A67P83181E-10.0F' PDF : 18 Pages View PDF
A67P83181/A67P73361 Series
AC Characteristics (Note 4)
(0°C ≤ TA ≤ 70°C, VCC = +2.5V± 5%)
Symbol
Parameter
-7.5
Min. Max.
-8.5
Min. Max.
-10.0
Min. Max.
Unit Note
Clock
tKHKH Clock cycle time
7.5
-
-8.5
-
10
-
ns
tKF Clock frequency
-
133
-
117
-
100 MHz
tKHKL Clock HIGH time
2.5
-
2.8
-
3.0
-
ns
tKLKH Clock LOW time
2.5
-
2.8
-
3.0
-
ns
Output Times
tKHQV Clock to output valid
-
6.5
-
7.5
-
8.5
ns
tKHQX Clock to output invalid
3.0
-
3.0
-
3.0
-
ns
tKHQX1 Clock to output in Low-Z
2.5
-
2.5
-
2.5
-
ns 1,2,3
tKHQZ Clock to output in High-Z
1.5
3.8
1.5
4.0
1.5
5.0
ns 1,2,3
tGLQV OE to output valid
-
3.5
-
3.5
-
4.0
ns
4
tGLQX OE to output in Low-Z
0
-
0
-
0
-
ns 1,2,3
tGHQZ OE to output in High-Z
-
3.5
-
3.5
-
4.0
ns 1,2,3
Setup Times
tAVKH
tEVKH
Address
Clock enable ( CEN)
1.5
-
2.0
-
2.0
-
ns
5
1.5
-
2.0
-
2.0
-
ns
5
tCVKH Control signals
1.5
-
2.0
-
2.0
-
ns
5
tDVKH Data-in
1.5
-
2.0
-
2.0
-
ns
5
Hold Times
tKHAX
tKHEX
Address
Clock enable ( CEN)
0.5
-
0.5
-
0.5
-
ns
5
0.5
-
0.5
-
0.5
-
ns
5
tKHCX Control signals
0.5
-
0.5
-
0.5
-
ns
5
tKHDX Data-in
0.5
-
0.5
-
0.5
-
ns
5
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured ±200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of
CLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK (when ADV/LD is LOW) to remain enabled.
PRELIMINARY (July, 2005, Version 0.0)
12
AMIC Technology, Corp.
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