A6B595 View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'A6B595' PDF : 10 Pages View PDF
A6B595
8-Bit Serial-Input DMOS Power Driver
PIN-OUT DIAGRAM
NO
CONNECTION
1
NC
LOGIC
SUPPLY
2
VDD
SERIAL
DATA IN
3
OUT 0 4
OUT1 5
OUT 2 6
OUT 3 7
REGISTER
CLEAR
8
CLR
OUTPUT 9 OE
ENABLE
GROUND 10
NC 20
NO
CONNECTION
19 GROUND
18
SERIAL
DATA OUT
17 OUT7
16 OUT6
15 OUT5
14 OUT 4
CLK 13 CLOCK
ST 12 STROBE
11 GROUND
Dwg. PP-029-12
Note that the A package (DIP) and the LW package
(SOIC) are electrically identical and share a common
terminal number assignment.
TERMINAL DESCRIPTIONS
Terminal No. Terminal Name
1
NC
2
LOGIC SUPPLY
3
SERIAL DATA IN
4-7
OUT0-3
8
CLEAR
9
OUTPUT ENABLE
10
11
12
13
14-17
18
19
20
GROUND
GROUND
STROBE
CLOCK
OUT4-7
SERIAL DATA OUT
GROUND
NC
Function
No internal connection.
(VDD) The logic supply voltage (typically 5 V).
Serial-data input to the shift-register.
Current-sinking, open-drain DMOS output terminals.
When (active) low, the registers are cleared (set low).
When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
Reference terminal for output voltage measurements (OUT0-3).
Reference terminal for output voltage measurements (OUT0-7).
Data strobe input terminal; shift register data is latched on rising edge.
Clock input terminal for data shift on rising edge.
Current-sinking, open-drain DMOS output terminals.
CMOS serial-data output to the following shift register.
Reference terminal for input voltage measurements.
No internal connection.
NOTE — Grounds (terminals 10, 11, and 19) must be connected together externally.
Allegro MicroSystems, Inc.
3
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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