A8351601F-40 View Datasheet(PDF) - AMIC Technology
Part Name
Description
MFG CO.
'A8351601F-40' PDF : 44 Pages View PDF
A8351601 Series
If a request is active and conditions are right for it to be
acknowledged, a hardware subroutine call to the requested
service routine will be the next instruction executed. The
call itself takes two cycles. Thus, a minimum of three
complete machine cycles elapsed between activation of an
external interrupt request and the beginning of execution of
the first instruction of the service routine. Figure 13 shows
response timings.
A longer response time results if the request is blocked by
one of the three previously listed conditions. If an interrupt
of equal or higher priority level is already in progress, the
additional wait time depends on the nature of the other
interrupt's service routine. If the instruction in progress is
not in its final cycle, the additional wait time cannot be
more than three cycles, since the longest instructions (MUL
and DIV) are only four cycles long. If the instruction in
progress is RETI or an access to IE or IP, the additional
wait time cannot be more than five cycles (a maximum of
one more cycle to complete the instruction in progress,
plus four cycles to complete the next instruction if the
instruction is MUL or DIV).
Thus, in a single-interrupt system, the response time is
always more than three cycles and less than nine cycles.
Other Information
Reset
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 15.
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1 has
been sampled at the RST pin; that is, for 19 to 31 oscillator
periods after the external reset signal has been applied to
the RST pin.
The internal reset algorithm writes 0s to all the SFRs
except the port latches, the Stack Pointer, and SBUF. The
port latches are initialized to FFH, the Stack Pointer to
07H, and SBUF is indeterminate. Table 11 lists the SFRs
and their reset values.
Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.
Table 11. Reset Values of the SFR's
SFR Name
Reset Value
PC
0000H
ACC
00H
B
00H
PSW
00H
SP
07H
DPTR
0000H
P0-P3
FFH
IP
XX000000B
IE
0X000000B
TMOD
00H
TCON
00H
T2CON
00H
TH0
00H
TL0
00H
TH1
00H
TL1
00H
TH2
00H
TL2
00H
RCAP2H
00H
RCAP2L
00H
SCON
00H
SBUF
Indeterminate
PCON
0XXX0000B
ADD
XXXXX000B
PWM1
X0000000B
PWM2
0XXX0000B
(July, 2002, Version 1.0)
31
AMIC Technology, Inc.
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