A8503 View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
A8503
Allegro MicroSystems
'A8503' PDF : 17 Pages View PDF
A8503
High Efficiency 6-Channel, 2 MHz, WLED/RGB Driver for
Medium Displays, with Integrated 55 V Power Switch
Input UVLO
The device is shut down when input voltage, VIN , falls below
VUVLO.
Thermal Shutdown Protection (TSD)
The device shuts down when junction temperature exceeds
165°C. If the MODE pin is low, the thermal shutdown will latch
the device off until EN is pulled low or UVLO is triggered. The
A8503 will recover automatically when the MODE pin is high
and the junction temperature falls below 120°C.
Fault Mode
The MODE pin controls the latching of faults as shown in the
Fault Mode table. Latched faults are reset when EN is pulsed low
or VIN falls below UVLO level.
A8503
SW
–
+ 1.23 V
OVP
disable
Latch
–
+ 22 kΩ
1.23 V
OVP
Fault Mode Table
Protection
Overvoltage Protection
Open Diode Protection
Pulse-by-Pulse Current
Limiting
Overcurrent Protection
Overtemperature
Protection
Shorted LED Protection
VIN UVLO
Soft Start Timeout
Figure 6. Overvoltage protection circuitry
MODE =
AGND
Latched
Latched
Auto-restart
Latched
Latched
Latched
No
Latched
MODE =
VIN
Auto-restart
Latched
Auto-restart
Auto-restart
Auto-restart
Latched
No
Auto-restart
Description
Fault occurs when OVP pin exceeds VOVP threshold. Used to protect the output voltage
from damaging the part.
Fault occurs when SW node exceeds the safe operating voltage of the boost DMOS
switch. Typical value is 57 V.
Fault occurs when the current through the DMOS switch exceeds ISWLIM, 2.7 A typical.
The DMOS switch is turned off on a cycle-by-cycle basis.
Fault occurs when the COMP pin exceeds the overcurrent detect threshold. Multiple
pulse-by-pulse current limits will cause the COMP pin voltage to rise. After a time
period determined by the COMP current and the compensation capacitor, the COMP
voltage will exceed the overcurrent detect threshold and force a fault.
Fault occurs when the die temperature exceeds the overtemperature threshold,
165°C typical.
Fault occurs when the LEDx pin voltage exceeds VSC, 18.7 V typical.
Fault occurs when VIN drops below VUVLO, 4.0 V typical. This fault resets all latched
faults.
Fault occurs if the IC is unable to finish soft start within approximately 131,000 clock
cycles (approximately 74 ms at 1.73 MHz) after EN is set high.
Allegro MicroSystems, Inc.
13
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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