A8503
High Efficiency 6-Channel, 2 MHz, WLED/RGB Driver for
Medium Displays, with Integrated 55 V Power Switch
Pin-out Diagram
NC 1
COMP 2
VIN 3
ISET 4
AGND 5
FSET 6
MODE 7
PAD
21 PGND
20 PGND
19 PWM
18 DGND
17 EN
16 FAULT
15 NC
(Top View)
Terminal List Table
Number
Name
1, 15, 22, 26
NC
2
COMP
3
VIN
4
ISET
5
AGND
6
FSET
7
MODE
8, 9, 10, 12,
13, 14
LEDx
11
LGND
16
¯F¯ ¯A ¯U ¯¯L¯ ¯T¯
17
EN
18
DGND
19
PWM
20, 21
PGND
23, 24
SW
25
OVP
–
PAD
Function
Not connected internally
Compensation pin; connect 1 μF capacitor to AGND or common star ground
Input supply for the IC; decouple with a 0.1 μF ceramic capacitor
Sets 100% current through LED string; connect RISET from ISET to AGND
Connect to common star ground
Set switching frequency; connect RFSET from FSET to AGND
Apply VIL for latching faults, apply VIH for auto-restart; see Fault Mode table
LED current sinks; connect unused LEDx pins to ground
Power ground pin for LEDx current sinks; connect to common star ground
During normal operation, this pin is high (high impedance); at a fault event, this pin pulls low
Device enable
Digital ground; connect to common star ground
PWM LED-current control; apply logic level PWM for dimming
Power ground; connect both pins to common star ground
DMOS switch drain node; tie both pins together on the PCB
Connect this pin to output capacitor +ve node through ROVP to enable overvoltage protection; select
ROVP > 10 kΩ (VOVP is 44 V typical)
Exposed thermal pad, common star ground for PGND, DGND, LGND, and AGND; connect to copper
plane of the application PCB for heat transfer
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com