A8508 View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
A8508
Allegro MicroSystems
'A8508' PDF : 28 Pages View PDF
A8508
Wide Input Voltage Range, High Efficiency
8-Channel Fault Tolerant LED Driver
LED Open Detect
When any LED string opens, the boost control circuit increases
the output voltage until it reaches the overvoltage protection
level. The OVP event causes any LED string that is below regula-
tion level to be disabled. After disabling the open string, the
output voltage returns to normal operating voltage. An EN low
signal will reset the LED string regulation lock.
Figure 25 shows a typical overvoltage condition when the output
voltage is disconnected from the LED load. Figure 26 shows an
extended view of the same situation. Figure 27 shows an OVP
condition created by a single open LED string.
Undervoltage Protection (UVP)
If the output voltage is shorted to ground the OVP pin will sense
an undervoltage condition (UVP). When UVP is sensed, the IC
sets the Fault flag low which, if used to interface to the output-
disconnect switch, will shut off the P-FET device. Figure 28 is a
schematic showing the input disconnect switch implementation.
VOUT
OVP level
IOUT
C2
VCOMP
C1
Fault occurrence
C3
VCOMP begins to decrease
t
Figure 25. OVP operation with all LEDx pins open. VOUT rises to the
overvoltage level and stays there until the IC is shut down; shows VOUT
(ch1, 20 V/div.), IOUT (ch2, 1 A/div.), and VCOMP (ch3, 2 V/div.),
t = 2 ms/div.
OVP limit is reached,
and string is removed
from control loop
VOUT (30 V)
VLEDx
LED string opens
C2
IOUT
Control loop reduces VOUT
to new regulation level
C3
t
Figure 27. OVP condition created by an open LED string; shows VOUT
(ch1, 2 V/div.), pin voltage VLEDx (ch2, 5 V/div.), and IOUT (ch3,
200 mA/div.), t = 2 ms/div.
VOUT
OVP level
IOUT
C2
C1
VCOMP
C3
Periodic switch node
bursts occur when all
LEDx pins are open
VSW
10 kΩ
VIN
VDR AO4421
L1
CIN (optional)
1 kΩ
1 kΩ
2N7002
FAULT
A8508
C4
t
Figure 26. Extended view of the OVP condition in figure 25; shows VOUT
(ch1, 20 V/div.), IOUT (ch2, 1 A/div.), VCOMP (ch3, 1 V/div.), and switch node
(VSW) (ch4, 20 V/div.), t = 10 ms/div.
Figure 28. Simplified schematic of an external disconnect switch
implementation.
Allegro MicroSystems, Inc.
15
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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