A8512
LED Backlight Driver for LCD Monitors and Televisions
Package ET 28-Contact QFN
5.00 ±0.15
28
1
2
A
5.00 ±0.15
0.30
1.15
28
1
0.50
3.15 4.80
29X D
0.08 C
0.25
+0.05
–0.07
0.50
0.73 MAX
B
2
1
28
3.15
C
SEATING
PLANE
0.90 ±0.10
3.15
4.80
C PCB Layout Reference View
For Reference Only; not for tooling use
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
3.15
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, Inc.
16
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com