Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

A8512 View Datasheet(PDF) - Allegro MicroSystems

Part Name
Description
MFG CO.
'A8512' PDF : 18 Pages View PDF
1 2 3 4 5 6 7 8 9 10 Next
A8512
LED Backlight Driver for LCD Monitors and Televisions
DRIVER 1
VREG7V 2
NC 3
VIN 4
NC 5
VBIAS 6
OVP 7
PAD
21 LED5
20 LED4
19 LGND
18 LGND
17 LED3
16 LED2
15 LED1
Pin-out Diagrams
EN 1
PGND 2
DRIVER 3
VREG7V 4
VIN 5
AGND 6
AGND 7
VBIAS 8
OVP 9
SENSE2 10
SENSE1 11
ISET 12
24 PWM
23 FAULT
22 LED6
21 LED5
20 LED4
19 LGND
18 LGND
17 LED3
16 LED2
15 LED1
14 COMP
13 FSET
EN 1
PGND 2
DRIVER 3
VREG7V 4
VIN 5
VBIAS 6
NC 7
OVP 8
SENSE2 9
SENSE1 10
ISET 11
AGND 12
PAD
24 DGND
23 PWM
22 FAULT
21 LED6
20 LED5
19 LED4
18 LGND
17 LED3
16 LED2
15 LED1
14 COMP
13 FSET
Package ET
Package LB
Package LP
Terminal List Table
Number
ET
LB
LP
26
1
1
28
2
2
1
3
3
2
4
4
4
5
5
11, 12
6, 7
12
6
8
6
7
9
8
8
9
10
13
14
15,16,17
18,19
20,21,22
23
24
25
3,5,27
PAD
10
11
12
13
14
15,16,17
18,19
20,21,22
23
24
9
10
11
13
14
15,16,17
18
19,20,21
22
23
24
7
PAD
Name
Function
EN Device Enable. Apply logic-high signal to enable, low to shut down.
PGND Power ground for external FET gate driver. Connect directly to RSC ground and to common star ground.
DRIVER Gate driver terminal to drive external MOSFET.
VREG7V Gate driver supply from internal voltage regulator. Bypass with 0.1 to 1 μF ceramic capacitor to PGND.
VIN Input supply voltage for the IC.
AGND Analog (signal) GND for the IC. Connect to common star ground.
VBIAS Bias supply voltage from internal regulator. Bypass with 0.1 to 1 μF ceramic capacitor to AGND
OVP
Overvoltage Protection terminal. Connect this pin to output capacitor through a resistor ROVP to set the
OVP threshold.
SENSE2
SENSE1
ISET
FSET
COMP
LED1-3
Connect to ground side of current sense resistor RSC.
Connect to high side of current sense resistor RSC.
Sets 100% Current through LED strings; connect RISET from ISET to AGND.
Sets switching frequency; connect RFSET from FSET to AGND.
Compensation pin; connect CCOMP (1 μF typical) capacitor to AGND.
LED current sinks; connect unused LEDx pins to ground to disable.
LGND LED current sink ground; connect to common star ground.
LED4-6 LED current sinks; connect unused LEDx pins to ground to disable.
¯F¯¯A¯¯U¯¯L¯¯T¯ This open-drain output is pulled low when fault condition occurs; connect to external pull-up resistor.
PWM Pulse width modulation LED-current control; apply logic level PWM for dimming.
DGND Digital ground for input control signals (EN and PWM); connect to common star ground.
NC Not connected electrically.
PAD Exposed pad. Solder to GND plane for enhanced thermal dissipation.
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]