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A8906CLB View Datasheet(PDF) - Allegro MicroSystems

Part Name
Description
MFG CO.
'A8906CLB' PDF : 12 Pages View PDF
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Terminal Name
LOAD SUPPLY
CD2
CWD
CST
OUTA
GROUND
OUTB
OUTC
CENTERTAP
BRAKE
CRES
FILTER
SECTOR DATA
LOGIC SUPPLY
OSCILLATOR
DATA OUT
GROUND
RESET
CHIP SELECT
CLOCK
DATA IN
CD1
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
TERMINAL FUNCTIONS
Function
VBB; the 5 V or 12 V motor supply.
One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.
Timing capacitor used by the watchdog circuit to disable the back-EMF compara-
tors during commutation transients, and to detect incorrect motor position.
Startup oscillator timing capacitor.
Power amplifier A output to motor.
Power and logic ground and thermal heat sink.
Power amplifier B output to motor.
Power amplifier C output to motor.
Motor centertap connection for back-EMF detection circuitry.
Active low turns ON all three sink drivers shorting the motor windings to ground.
External capacitor and resistor at BRAKE provide brake delay.
External reservoir capacitor used to hold charge to drive the source drivers
gates. Also provides power for brake circuit.
Analog voltage input to control motor current. Also, compensation node for
internal speed control loop.
External tachometer input. Can use sector or index pulses from disk to provide
precise motor speed feedback to internal frequency-locked loop.
VDD; the 5 V logic supply.
Clock input for the speed reference counter. Typical max. frequency is 10 MHz.
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real
time, controlled by 2-bit multiplexer in serial port.
Power and logic ground and thermal heat sink.
When pulled low forces the chip into sleep mode; clears all serial port bits.
Strobe input (active low) for data word.
Clock input for serial port.
Sequential data input for the serial port.
One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.
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