A8925CEB View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
A8925CEB
Allegro MicroSystems
'A8925CEB' PDF : 8 Pages View PDF
8925
3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER
WITH LINEAR CURRENT CONTROL
AND POWER DMOS OUTPUTS
across RS that equals RS • ILOAD/1200. This
sense voltage (VSENSE) is compared to a ref-
erence voltage (VREF) and an error voltage is
developed that is gated in by the sequential
control logic to drive the gate of the appropri-
ate output sink transistor. A
transconductance control function is thus re-
alized where IOUT = VREF • 1200/RS. External
components C1, C2, R1, R2, and R3 are com-
pensation components used to obtain optimal
response and settling of the current control
loop. Information on how to select these
components is available.
FAULT. The FAULT terminal when low
indicates the presence of one of three fault
conditions:
A) An under-voltage condition
on the logic supply. The
trip point for this function is
between 8 and 9.5 volts.
B) An invalid Hall input combi-
nation … all inputs High or
all inputs Low.
C) An excessive device
junction temperature. The
thermal shutdown circuitry
disables the output drivers
in addition to forcing the
FAULT output signal low.
TACH and POLE. In order to develop a
low-jitter tachometer signal (TACH) for use in
controlling motor speed, the A8925CEB di-
vides the frequency of the H1 input by the
number of poles in the motor. This elimi-
nates the jitter caused by variations in Hall-
effect device placement , sensitivity, and
magnet strengths by always changing state
when looking at the same magnet/sensor
pair. The resulting TACH signal changes state
every mechanical revolution of the motor.
The POLE input sets the TACH signal for four-
pole motors when Low or eight-pole motors
when High.
HALL INPUTS (H1, H2, H3). The A8925CEB is configured for use
with open-collector Hall-effect devices. Internal 25 kΩ pull up resistors
to 10 volts are connected to these inputs.
ENABLE. The ENABLE terminal when Low puts the device in a
low current consumption, power-down mode. When ENABLE is High
the device is active.
BRAKE. When the BRAKE input goes Low the output source driv-
ers are disabled and the gates of the sink drivers are pulled high and
left floating. This achieves optimum passive braking performance
since the sink power DMOS output drivers are ON until the motor has
fully completed braking. The braking control circuitry operates off the
load supply (VBB) to allow it to remain operational during power loss by
using the back-EMF voltage of the motor as it’s supply.
LOAD SUPPLY (VBB). This terminal is the power supply connec-
tion for the power output drivers and braking control circuitry. This ter-
minal should be decoupled with a large-value capacitor to absorb load
currents dumped back into the supply during the de-energization of
motor windings. These currents can cause the supply voltage to ex-
ceed the maximum voltage rating of the device if not properly
decoupled. The intrinsic ground clamp and flyback diodes will rectify
the motor’s back-EMF voltage during power loss. In applications were
use of the motor’s back-EMF voltage is desired a series diode should
be used to isolate this terminal from the logic supply (VCC). This is to
avoid dumping the charge back into the supply and therefor clamping
the voltage available from rectification of the motor’s back-EMF
voltage.
LOGIC SUPPLY (VCC). This is the 12 volt supply terminal for the
A8925CEB and powers all circuitry except the power outputs and
brake control circuitry.
LOGIC GROUND. This must be connected to the power ground
terminals in systems that do not use separate power and logic
grounds.
POWER GROUND. Terminals 7 through 17 and 29 through 39
are webbed together and attach to the die mounting area to form a low
thermal resistance path to allow heat to be conducted out of the de-
vice. The power dissipation of the package can be further enhanced
by soldering these terminals to a large area of copper foil on the
printed wiring board.
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