SwitchRegTM
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
PTOTAL = IO2 · RDS(ON)H + IQ · VIN
Since RDS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the θJA for the TDFN3-12 and
TSOPJW-12 packages, which is 50°C/W and 160°C/W
respectively.
TJ(MAX) = PTOTAL · ΘJA + TAMB
PRODUCT DATASHEET
AAT1112
1.5A, 1.4MHz Step-Down Converter
Layout
The suggested PCB layout for the AAT1112 is shown in
Figures 2 and 3. The following guidelines should be used
to help ensure a proper layout.
1. The input capacitor (C1) should connect as closely as
possible to VP and PGND.
2. C2 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX pin should be as
short as possible.
3. The feedback trace or FB pin should be separate
from any power trace and connect as closely as pos-
sible to the load point. Sensing along a high-current
load trace will degrade DC load regulation.
4. The resistance of the trace from the load return to
PGND should be kept to a minimum. This will help to
minimize any error in DC regulation due to differ-
ences in the potential of the internal signal ground
and the power ground.
5. Connect unused signal pins to ground to avoid
unwanted noise coupling.
SYNC
Vin
LL PWM
GND
GND
L1 C1
On
LX
Vout
Off
U1
R3 Enable
C3
C2 R2
GND
AAT1112
AnalogicTech
Figure 2: AAT1112 Evaluation Board Top Side Layout.
14
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1112.2007.11.1.2