AAT1120IES-0.6-T1 View Datasheet(PDF) - Skyworks Solutions
Part Name
Description
MFG CO.
'AAT1120IES-0.6-T1' PDF : 19 Pages View PDF
Thermal Calculations
There are three types of losses associated with the
AAT1120 step-down converter: switching losses, con-
duction losses, and quiescent current losses. Conduction
losses are associated with the RDS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of the losses is
given by:
PTOTAL
=
IO2
·
(RDS(ON)H
·
VO
+
RDS(ON)L
VIN
·
[VIN
-
VO])
+ (tsw · FS · IO + IQ) · VIN
IQ is the step-down converter quiescent current. The
term tsw is used to estimate the full load step-down con-
verter switching losses.
For the condition where the step-down converter is in
dropout at 100% duty cycle, the total device dissipation
reduces to:
PTOTAL = IO2 · RDS(ON)H + IQ · VIN
Since RDS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range.
Given the total losses, the maximum junction tempera-
ture can be derived from the JA for the STDFN22-8 pack-
age which is 50°C/W.
TJ(MAX) = PTOTAL · ΘJA + TAMB
DATA SHEET
AAT1120
500mA Step-Down Converter
Layout
The suggested PCB layout for the AAT1120 in an
STDFN22-8 package is shown in Figures 2, 3, and 4. The
following guidelines should be used to help ensure a
proper layout.
1. The input capacitor (C1) should connect as closely
as possible to VP (Pin 1), PGND (Pin 8), and GND
(Pin 3)
2. C2 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX pin (Pin 7) should
be as short as possible. Do not make the node small
by using narrow trace. The trace should be kept
wide, direct and short.
3. The feedback pin (Pin 4) should be separate from
any power trace and connect as closely as possible
to the load point. Sensing along a high-current load
trace will degrade DC load regulation. Feedback
resistors should be placed as closely as possible to
the FB pin (Pin 4) to minimize the length of the high
impedance feedback trace. If possible, they should
also be placed away from the LX (switching node)
and inductor to improve noise immunity.
4. The resistance of the trace from the load return to
PGND (Pin 8) and GND (Pin 3) should be kept to a
minimum. This will help to minimize any error in DC
regulation due to differences in the potential of the
internal signal ground and the power ground.
5. A high density, small footprint layout can be achieved
using an inexpensive, miniature, non-shielded, high
DCR inductor.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201973B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • March 15, 2013
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