AAT1142 View Datasheet(PDF) - Advanced Analogic Technologies
Part Name
Description
MFG CO.
'AAT1142' PDF : 21 Pages View PDF
SwitchRegTM
PRODUCT DATASHEET
AAT1142
800mA Voltage-Scaling Step-Down Converter
VOUT
1
2
JP1
LX
C4
(optional)
0.1μF
C2
10μF
L1
2.2μH
VIN
VIN
(optional) R5
1.8K
SDA
1
SCL
2
JP2
R4
1.8K
U1
1
LX
12
VIN
2
PGND
11
AGND
3
10
MODE/SYNC AGND
4
SDA
9
AGND
5
SCL
8
AGND
6
EN/SET
7
FB
AAT1142
VIN
TSOPJW-12
U1 AAT1142 TSOPJW-12
L1 CDRH2D14/2R2
C1 4.7μF 10V 0805 X5R
C2 10μF 10V 0805 X5R
C3 10μF optional
C4 0.1μF optional
R1 0Ω 0603
R2 optional 0603
R3 10K 0603
R4, R5 1.8K 0603
VIN
C1
4.7μF
VIN
C3
(optional)
10μF
R1
0
R3
10K
1
2
3
JP3
R2
(optional)
Figure 1: AAT1142 Evaluation Board Schematic.
Applications Information
The AAT1142 output voltage may be programmed from
0.6V to 2.0V through I2C or S2Cwire serial interface.
When using I2C or S2Cwire, the output voltage can be
programmed across the entire output voltage range or in
increments as small as ±50mV (see Figure 2).
I2C Serial Interface
The AAT1142 is compatible with the I2C interface, which
is a widely used two-line serial interface. The I2C two-
wire communications bus consists of SDA and SCL lines.
SDA provides data, while SCL provides clock input. SDA
data consists of an address bit sequence followed by a
data bit sequence. SDA data transfer is synchronized to
SCL rising clock edges.
When using the I2C interface, EN/SET is pulled high to
enable the output or low to disable the output. To ensure
a disable event, the EN/SET pulse width must be greater
than the latch time (500μs maximum).
The I2C serial interface requires a master to initiate all
the communications with slave devices. The I2C protocol
is a bidirectional bus allowing both read and write actions
to take place; while the AAT1142 is a slave device and
only supports the write protocol.
The AAT1142 is a receiver-only (or write-only) slave
device and the Read / Write (R/W) bit is set low. The
AAT1142 address is preset to 0x14 (Hex).
I2C START and STOP Conditions
START and STOP conditions are initialized by the I2C bus
master. The master determines the START (beginning)
and STOP (end) of a transfer with the slave device. Prior
to initiating a START or after STOP, both the SDA and
SCL lines are in bus-free mode. Bus-free mode is when
SDA and SCL are both in the high state (see Figure 3).
I2C Address Bit Map
Figure 4 illustrates the address bit map format. The 7-bit
address is sent with the Most Significant Bit (MSB) first
and is valid when SCL is high. This is followed by the R/W
bit in the Least Significant Bit (LSB) location. The R/W
bit determines the direction of the transfer (‘1’ for read,
‘0’ for write). The AAT1142 is a write-only device and
this bit must be set low when communicating with the
AAT1142. The Acknowledge bit (ACK) is set to low by the
AAT1142 slave to acknowledge receipt of the address.
12
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1142.2009.08.1.1
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