AAT3171 View Datasheet(PDF) - Analog Technology Inc
Part Name
Description
MFG CO.
'AAT3171' PDF : 19 Pages View PDF
Capacitor area is another contributor to ESR.
Capacitors that are physically large will have a lower
ESR when compared to an equivalent material
smaller capacitor. These larger devices can improve
circuit transient response when compared to an
equal value capacitor in a smaller package size.
Thermal Protection
The AAT3171 has a thermal protection circuit that
will shut down the charge pump if the die tempera-
ture rises above the thermal limit, as is the case
during a short-circuit of the OUT pin.
PCB Layout
To achieve adequate electrical and thermal per-
formance, careful attention must be given to the
PCB layout. In the worst-case operating condition,
the chip must dissipate considerable power at full
load. Adequate heat-sinking must be achieved to
ensure intended operation.
Figure 4 illustrates an example of an adequate
PCB layout. The bottom of the package features an
exposed metal paddle. The exposed paddle acts,
thermally, to transfer heat from the chip and, elec-
trically, as a ground connection.
The junction-to-ambient thermal resistance (θJA) for
the package can be significantly reduced by follow-
ing a couple of important PCB design guidelines.
The PCB area directly underneath the package
should be plated so that the exposed paddle can
be mated to the top layer PCB copper during the
re-flow process. This area should also be connect-
ed to the top layer ground pour when available.
Further, multiple copper plated thru-holes should
be used to electrically and thermally connect the
top surface paddle area to additional ground
plane(s) and/or the bottom layer ground pour.
The chip ground is internally connected to both the
paddle and the GND pin. The GND pin conducts
large currents and it is important to minimize any
differences in potential that can result between the
GND pin and exposed paddle. It is good practice to
connect the GND pin to the exposed paddle area
using a trace as shown in Figure 4.
14
AAT3171
High Current, High Efficiency
Charge Pump with Auto-Timer
Figure 4: Example PCB Layout.
The flying capacitors C1 and C2 should be con-
nected close to the chip. Trace length should be
kept short to minimize path resistance and potential
coupling. The input and output capacitors should
also be placed as close to the chip as possible.
Evaluation Board User Interface
The user interface for the AAT3171 evaluation
board is provided by 3 buttons and a couple of con-
nection terminals. The board is operated by supply-
ing external power and pressing individual buttons
or button combinations. The table below indicates
the function of each button or button combination.
To power-on the evaluation board, connect a power
supply or battery to the DC- and DC+ terminals.
Make the board's supply connection by positioning
the J1 jumper to the ON position. A red LED indi-
cates that power is applied.
The evaluation board is made flexible so that the
user can disconnect the enable line from the micro-
controller and apply an external enable signal. By
removing the jumper from J2, an external enable
signal can be applied to the board. Apply the exter-
nal enable signal to the ON pin of the J2 terminal.
When applying an external enable signal, consider-
ation must be given to the voltage level. The exter-
nally applied voltage cannot exceed the supply
voltage that is applied to the VIN pins of the device
(i.e., DC+).
3171.2007.03.1.1
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