ACD81024 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'ACD81024' PDF : 17 Pages View PDF
7. SIGNAL DESCRIPTION
The interface signals of ACD81024 can be divided
into four groups. The description of all kinds of
signals in each group are shown below:
Table 7.1 - 10Base-T Interface Group:
Mnemonic
TYPE I/O Active
Description
TXP_0 ~ TXP_23 DIFF O
Ethernet 10Base-T twisted pair Transmit Output Positive
TXN_0 ~ TXN_23 DIFF O
Ethernet 10Base-T twisted pair Transmit Output Negative
RXP_0 ~ RXP_23 DIFF I
Ethernet 10Base-T twisted pair Receive Input Positive
RXN_0 ~ RXN_23 DIFF I
Ethernet 10Base-T twisted pair Receive Input Negative
Table 7.2 - Configuration Interface Group
Mnemonic TYPE I/O Active
Description
LNKE
CMOS I HIGH
Link integrity detection function enable
POLE
CMOS I HIGH
Automatic polarity detection and correction function enable
SQLE
CMOS I HIGH
Smart squelch intelligence function enable
DMPE
CMOS I HIGH
Periodic dumping function enable
WDGE CMOS I HIGH
Transmit Time Watchdog function enable
Table 7.3 - LED Interface Group
Mnemonic TYPE I/O Active
LNK
CMOS O HIGH
XMT
CMOS O HIGH
RCV
CMOS O HIGH
COL
CMOS O HIGH
BSY
CMOS O HIGH
JBR
CMOS O HIGH
ADDR CMOS O HIGH
FBE
CMOS O HIGH
LEDVLD CMOS O HIGH
LEDCLK CMOS O
Description
Link status indication signal
Transmit indication signal
Receive indication signal
Collision indication signal
Congestion control indication signal
Jabber error indication signal
Port address learned status indication signal
Frame bit error (FCS error or alignment error) indication signal
LED valid signal
LED clock signal
Table 7.4 - Misc. Signal Group
Mnemonic TYPE I/O Active
DVDD
I
AVDD
I
DVSS
I
AVSS
I
CLK80
CMOS I
RESETN CMOS I LOW
Description
+5V power input for digital circuitry
+5V power input for analog circuitry
Ground power input for digital circuitry
Ground power input for analog circuitry
System clock signal from a 80.000Mhz clock oscillator
System Reset Negative, low active
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.
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