Capacitor on FAULT Pin for High CMR
Rapid common mode transients can affect the fault pin
voltage while the fault output is in the high state. A 330
pF capacitor should be connected between the fault pin
and ground to achieve adequate CMOS noise margins at
the specified CMR value of 15 kV/µs. The added capaci-
tance does not increase the fault output delay when a
desaturation condition is detected.
Pull-up Resistor on FAULT Pin
The FAULT pin is an open collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Also the FAULT output can be wire ‘OR’ed together with
other types of protection (e.g. over-temperature, over-
voltage, over-current ) to alert the microcontroller.
Other Possible Application Circuit (Output Stage)
1 VS
2 VCC1
3 FAULT
4 VS
5 CATHODE
6 ANODE
7 ANODE
8 CATHODE
VE 16
VLED 15
DESAT 14
0.1µF 0.1µF
VCC2 13
VEE 12
VOUT 11
VCLAMP 10
0.1µF
Optional R1
VEE 9
Optional R2
RG
+_
Q1
RPULL-DOWN
+_
*
Q2
+ HVDC
+
VCE
-
3-PHASE
AC
+
VCE
-
- HVDC
Figure 37. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used) VCLAMP is
used as secondary gate discharge path. * indicates component required for negative gate drive topology
1 VS
2 VCC1
3 FAULT
4 VS
5 CATHODE
6 ANODE
7 ANODE
8 CATHODE
VE 16
VLED 15
DESAT 14
0.1µF 0.1µF
VCC2 13
VEE 12
VOUT 11
VCLAMP 10
0.1µF
Optional R1
VEE 9
Optional R2
RG
+_
Q1
RPULL-DOWN
+_ *
Q2
R3
+ HVDC
+
VCE
-
3-PHASE
AC
+
VCE
-
- HVDC
Figure 38. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application.
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