ACPL-336J-000E View Datasheet(PDF) - Avago Technologies

Part Name

Description

MFG CO.

ACPL-336J-000E

2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection, Active Miller Clamping, Fault and UVLO Status Feedback

Avago Technologies 

Prev 11 12 13 14 15 16 17 18

DESAT Fault Detection Blanking Time

The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to

allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is con-

trolled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor.

The nominal blanking time is calculated in terms of external capacitance (CBLANK, see Figure 20 and Figure 21),

FAULT threshold voltage (VDESAT), and DESAT charge current (ICHG) in addition to an internal DESAT blanking time

(tDESAT(BLANKING)).

tBLANK = CBLANK × (VDESAT/ICHG) + tDESAT(BLANKING)

Description of Operation during DESAT Fault Condition

1. DESAT terminal monitors IGBT’s VCE voltage.

2. When the voltage on the DESAT terminal exceeds 7 V, a weak pull-down in the output stage(IOLF) will turn on to‘softly’

turn off the IGBT. When the gate voltage falls below VEE+2 V, the Miller Clamp will turn on to clamp the IGBT gate to

VEE.

3. FAULT output goes low, notifying the microcontroller of the fault condition.

4. Microcontroller takes appropriate action.

5. When tDESAT(MUTE) expires, LED input needs to be kept low for tDESAT(RESET) before fault condition is cleared. FAULT

status will return to high.

6. Output (VOUT) starts to respond to LED input after fault condition is cleared.

tDESAT(MUTE)

LED1 IF

VOUT

VDESAT

FAULT

7V

tDESAT(BLANKING)

tDESAT(90%)

90%

10%

tDESAT(10%)

tDESAT(LOW)

tDESAT(BLANKING)

50%

tDESAT(FAULT)

Figure 24. DESAT fault state timing diagram

tDESAT(RESET)

Selecting the Gate Resistor (RG)

Step 1: Calculate RG minimum from the IO(PEAK) specification. The IGBT and RG in Figure 20 can be analyzed as a simple

RC circuit with a voltage supplied by ACPL-336J.

RG

≥

VCC − VEE

I O(PEAK)

− R DS,OH(MIN)

=

30 − 0 V

2.5 A

− 0.5

Ω

= 11.5 Ω

RG

≥

V CC − VEE

I O(PEAK)

− R DS,OL(MIN)

or

=

30

2

−

.5

0V

A

− 0.2 Ω

= 11.8 Ω

The external gate resistor, RG and internal minimum turn-on resistance, RDSON will ensure the output current will not

exceed the device absolute maximum rating of 2.5 A. In this case, we will use worst-case RG ≥ 11.8 Ω.

16

Share Link: