ACPL-38JT-000E View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ACPL-38JT-000E' PDF : 33 Pages View PDF
Printed Circuit Board Layout Considerations
Adequate spacing should always be maintained between
the high voltage isolated circuitry and any input refer-
enced circuitry. Care must be taken to provide the same
minimum spacing between two adjacent high-side
isolated regions of the printed circuit board. Insufficient
spacing will reduce the effective isolation and increase
parasitic coupling that will degrade CMR performance.
The placement and routing of supply bypass capacitors
requires special attention. During switching transients,
the majority of the gate charge is supplied by the bypass
capacitors. Maintaining short bypass capacitor trace
lengths will ensure low supply ripple and clean switching
waveforms. See Figure 77A.
Bypass Capacitors should be placed in between these
pins: VCC2 to VE, VE to VEE, VCC1 to GND1 and VCC2 to VEE.
Ground plane connections are necessary for PIN1 (GND1)
and PIN 9 (VEE) in order to achieve maximum power as the
ACPL-38JT is designed to dissipate the majority of heat
generated through these pins. Actual power dissipation
will depend on the application environment (PCB layout,
airflow, part placement, etc. (See Figure 77B and 77C).
VE should have direct connection (Kelvin connection) to
IGBT Emitter to avoid switching noise on the ground line
affecting accurate DESAT voltage sensing. See Figure77C.
Bypass Cap
C13
Bypass Cap
C1, C2, C4
Ground Plane for GND1
(Pin 1)
ACPL-36JV/38JT
Top Gate
Driver (U1)
Figure 77a. Bypass Capacitors
Ground Plane for VEE (Pin 9)
Board Isolation
Figure 77b. Ground Plane
Kelvin Connection between VEE and IGBT Emitter
Figure 77c. Kelvin Connection between VEE and IGBT Emitter
32
IGBT
Emitter
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