ACPL-H342 View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
'ACPL-H342' PDF : 19 Pages View PDF
R
1 ANODE
+_
2 NC
R
3 CATHODE
4 NC
VCC 8
VOUT 7
VCLAMP 6
VEE 5
RG
1µF
VCC=18V
+_
Q1
Q2
Figure 33. Recommended application circuit with split resistors LED drive and active Miller Clamp.
+ HVDC
+
VCE
-
3-PHASE
AC
+
VCE
-
-HVDC
Active Miller Clamp
A Miller clamp allows the control of the Miller current
during a high dV/dt situation. And it can also eliminate
the use of a negative supply voltage by quickly discharg-
ing the large gate capacitance of IGBT to low level without
affecting the IGBT turn-off characteristics. During turn-off,
the gate voltage is monitored and the clamp output is
activated when gate voltage goes below 2.3V (relative to
VEE). The clamp voltage is VOL+2.5V typ for a Miller current
up to 2.5 A. The clamp is disabled when the LED input is
triggered again.
AN5314 application note describes how the clamp reduces
the parasitic turn-on effect due to the Miller capacitor and
at the same time eliminates the need of a negative power
supply.
The Miller pin should be connected to VEE when not in use.
Rail-to-Rail Output
Figure 34 shows a typical gate driver’s high current
output stage with 3 bipolar transistors in darlington con-
figuration. During the output high transition, the output
voltage rises rapidly to within 3 diode drops of VCC. To
ensure the VOUT is at VCC in order to achieve IGBT rated
VCE(ON) voltage. The level of VCC will be need to be raised
to beyond VCC+3(VBE) to account for the diode drops. And
to limit the output voltage to VCC, a pull-down resistor,
RPULL-DOWN between the output and VEE is recommended
to sink a static current while the output is high.
ACPL-H342 uses a power NMOS follower stage to deliver
the initial large current and a smaller PMOS to pull it to VCC
to achieve Rail-to-Rail output voltage as shown in Figure
35. This ensures that the IGBT’s gate voltage is driven to
the optimum intended level with no power loss across
IGBT even when an unstable power supply is used.
ANODE 1
NC 2
CATHODE 3
NC 4
8 VCC
7
VOUT
6
VEE
5
RG
RPULL-DOWN
Figure 34. Typical gate driver with output stage in darlington configuration
ANODE 1
NC 2
CATHODE 3
NC 4
VVCCLLAAMMPP
8 VCC
7 VOUT
6 VCLAMP
5 VEE
Figure 35. ACPL-H342 with NMOS and PMOS output stage for Rail-to-Rail output voltage
15
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