ACS716 View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
ACS716
Allegro MicroSystems
'ACS716' PDF : 22 Pages View PDF
ACS716
120 kHz Bandwidth, High Voltage Isolation
Current Sensor with Integrated Overcurrent Detection
Functional Description (Non-Latching Versions)
Overcurrent Fault Operation
The primary concern with high-speed fault detection is that noise
may cause false tripping. Various applications have or need to
be able to ignore certain faults that are due to switching noise or
other parasitic phenomena, which are application dependant. The
problem with simply trying to filter out this noise in the main sig-
nal path is that in high-speed applications, with asymmetric noise,
the act of filtering introduces an error into the measurement.
To get around this issue, and allow the user to prevent the fault
signal from going low due to noise, a circuit was designed to slew
the ¯F¯A¯¯U¯¯L¯¯T¯ pin voltage based on the value of the capacitor from
that pin to ground. Once the voltage on the pin falls below 2 V, as
established by an internal reference, the fault output is pulled to
ground quickly with an internal N-channel MOSFET.
Fault Walk-through
The following walk-through references various sections and
attributes in the figure below. This figure shows different
fault set/reset scenarios and how they relate to the voltages on
the ¯F¯A¯¯U¯¯L¯¯T¯ pin, FAULT_EN pin, and the internal Overcurrent
(OC) Fault node, which is invisible to the customer.
1. Because the device is enabled (FAULT_EN is high for a mini-
mum period of time, the Fault Enable Delay, tFED , and there is
an OC fault condition, the device ¯F¯A¯¯U¯¯L¯¯T¯ pin starts discharging.
2. When the ¯F¯A¯¯U¯¯L¯¯T¯ pin voltage reaches approximately 2 V, an
internal NMOS device pulls the ¯F¯A¯¯U¯¯L¯¯T¯ pin voltage to approx-
imately 0 V. The rate at which the ¯F¯A¯¯U¯¯L¯¯T¯ pin slews downward
(see [4] in the figure) is dependent on the external capacitor,
COC, on the ¯F¯A¯¯U¯¯L¯¯T¯ pin.
3. When the FAULT_EN pin is brought low, the ¯F¯A¯¯U¯¯L¯¯T¯ pin
starts resetting if FAULT_EN is low for a time period greater
than tOCH . The internal NMOS pull-down turns off and an
internal PMOS pull-up turns on.
4. The slope, and thus the delay to pull the fault low is controlled
by the capacitor, COC, placed on the ¯F¯A¯¯U¯¯L¯¯T¯ pin to ground.
During this portion of the fault (when the ¯F¯A¯¯U¯¯L¯¯T¯ pin is
between VCC and 2 V), there is a 3 mA constant current sink,
which discharges COC. The length of the fault delay, t, is equal
to:
t = COC ( VCC – 2 V )
3 mA
(2)
where VCC is the device power supply voltage in volts, t is in
seconds and COC is in Farads. This formula is valid for RPU
equal to or greater than 330 kΩ. For lower-value resistors,
the current flowing through the RPU resistor during a fault
event, IPU , will be larger. Therefore, the current discharging
the capacitor would be 3 mA – IPU and equation 1 may not be
valid.
5. The ¯F¯A¯¯U¯¯L¯¯T¯ pin did not reach the 2 V latch point before the
OC fault condition cleared. Because of this, the fixed 3 mA
current sink turns off, and the internal PMOS pull-up turns on
to recharge COC through the ¯F¯A¯¯U¯¯L¯¯T¯ pin.
6. This curve shows VCC charging external capacitor COC
through the internal PMOS pull-up. The slope is determined
by COC.
7. At this point there is a fault condition, and the part is enabled
before the ¯F¯A¯¯U¯¯L¯¯T¯ pin can charge to VCC. This shortens the
user-set delay, so the fault gets pulled low earlier. The new
delay time can be calculated by equation 1, after substituting
the voltage seen on the ¯F¯A¯¯U¯¯L¯¯T¯ pin for VCC.
VCC
FAULT
(Output)
2V
0V
FAULT_EN
(Input)
OC Fault
Condition
(Active High)
1
4
2
1
1
tFED
6
46
5
4
2
3
Time
7
6
4
2
Allegro MicroSystems, LLC
17
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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