ACS760ELF-20B View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
MFG CO.
'ACS760ELF-20B' PDF : 15 Pages View PDF
ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Soft Short Circuit Fault Operation
The timing diagram in figure 2 shows the characteristic opera-
tion of the ACS760 when the current load on the 12 V system bus
jumps from the 19 to 20 A level to the 40 A level. The 40 A load
is typically indicative of a soft short circuit on the ILOAD side of
the external MOSFET.
In figure 2, the system power supply bus reaches the nominal
steady state level of 12 V before the EN pin (Enable pin, active
high) of the ACS760 transitions to the high state at time tEN1.
Note that when the EN pin is in the low state, the GATE pin is
actively pulled low. However, as shown in the timing diagram,
the voltage on the GATE pin increases with a positive slope after
the EN pin transitions to the high state. The ramp rate of the
GATE pin is controlled by the value of the capacitor connected to
the CG pin.
At a certain GATE voltage, current begins to flow through the
external protection MOSFET, S1, and this current increases as the
GATE voltage increases. The voltage at the VIOUT pin, which is
the current sensor output voltage of the ACS760, proportionally
tracks the current that flows through the MOSFET.
In the timing diagram the system is in normal, steady state
operation up until the time tINIT_F. At tINIT_F the current load
on the 12 V power supply increases from 19.2 A to 40 A and the
ACS760 internally registers both a 240 V*A fault condition and
an IPF fault condition. In this example, the ISET voltage was set
at 3.0 V, which corresponds to a 40 A fault threshold. At tINIT_F,
the voltage on the OPDLY and OCDLY pins increases with a
constant slope. The slope of the voltage on the two delay pins is
controlled by the value of the capacitor connected to each pin.
In this case the capacitor on the OCDLY pin is smaller than the
capacitor on the OPDLY pin and the voltage on the OCDLY pin
ramps much faster than the voltage on the OPDLY pin (both pins
are connected to separate 20 μA current sources). The voltages on
each delay pin continues to increase with a constant slope until
either:
• Either the OPDLY or the OCDLY pin voltages reach a threshold
of 3.85 V (if this occurs, the FAULT signal is latched in the low
state), or
• The current load of the system falls below 20 A for the OPDLY
pin and 40 A for the OCDLY pin
In figure 2 a short circuit fault event is detected at t40A_F. At
this time, the FAULT signal transitions to the low state and the
GATE pin is pulled to ground. The FAULT state is latched and
the chip will pull down the GATE voltage until the EN pin of the
ACS760 transitions to the low state and then back to the high
state. As shown in the timing diagram, certain ACS760 signals
(the FAULT signal and the OCDLY pin voltage) are reset when
the EN pin transitions to the low state. These signals are reset in
order to guarantee normal device operation (soft start and fault
monitoring) when the EN signal transitions back to the high state.
Figure 2. Timing Diagram for 30 to 40 A Load Fault
Allegro MicroSystems, Inc.
9
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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