ACS8509 SETS
ADVANCED COMMUNICATIONS
Table 14 Register Description (cont...)
FINAL
DATASHEET
Addr.
(Hex)
Register Name
Description
38 cnfg_T0_output_enable This register contains several individual configuration fields, as follows:
Default Value (Bin)
Bit 7
Unused.
Bit 6
=1
SONET mode selected for Dig2,
=0
SDH mode selected for Dig2 (default)
- see register cnfg_T0_output_frequencies,
Bit 5
=1
SONET mode selected for Dig1,
=0
SDH mode selected for Dig1 (default)
- see register cnfg_T0_output_frequencies.
Bit 4
=1
Output port O2 enabled (default),
=0
Output port O2 disabled**
- see register cnfg_T0_output_frequencies.
00011111
Bit 3
Set to 0.
Bit 2
=1
Output port O3 enabled (19.44 MHz*) (default),
=0
Output port O3 disabled**.
Bits (1:0) Set to 0.
39 cnfg_T0_output_
frequencies
Notes:
* Defaults frequencies are changed to multiples of E1/T1 if the appropriate bit of the
cnfg_control1 register is set to 1. For details, see Table 10.
** “Disabled” means that the output port holds a static logic value (the port is not Tri-
stated).
This register holds the frequency selections for each output port, as detailed below.*
Bits (7:6) Dig2:
00 1544 kHz/2048 kHz (default),
01 3088 kHz/4096 kHz,
10 6176 kHz/8192 kHz,
11 12352 kHz/16384 kHz.
Bits (5:4) Dig1:
00 1544 kHz/2048 kHz (default),
01 3088 kHz/4096 kHz,
10 6176 kHz/8192 kHz,
11 12352 kHz/16384 kHz
Bits (3:2) Unused.
Bits (1:0)O2
00 6.48 MHz (default)
01 25.92 MHz
10 19.44 MHz
11 Dig1.
0000100
For Dig1/Dig2 the frequency values are shown for SONET/SDH. They are selected via
the SONET/SDH bits in register cnfg_T0_output_enable.
Note:
* The above frequencies are changed to multiples of E1/T1 if the appropriate bit of
the cnfg_control1 register is set to 1. For details, see Table 10.
Revision 2.00/January 2006 © Semtech Corp.
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