ACS8510 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8510' PDF : 69 Pages View PDF
ACS8510 Rev2.1 SETS
ADVANCED COMMUNICATIONS
Figure 4. Minimum Input Jitter Tolerance (DS1/E1)
(for inputs supporting G.783 compliant sources)
FINAL
Peak-to-peak jitter and wander amplitude (log
scale)
A1
A2
f1
f2
f3
Jitter and wander frequency (log scale)
f4
Table 7. Amplitude and Frequency Values for Jitter Tolerance
Ty p e
Spec.
Amplitude
(UI pk-pk)
Fr eq u en cy
(Hz)
A1
A2 F1 F2
F3
F4
DS1
G R - 1 24 4 - C O R E
E1
ITU G.823
5
0.1 10 500 8k
40k
1.5
0.2 20 2.4k 18k 100k
between
devices).
Using
the
cnfg_differential_outputs register, outputs TO6
and T can be made to be LVDS or PECL
O7
compatible.
Frame Sync and Multi-Frame Sync Clocks (Part of
T OUT0)
Frame Sync (8 kHz) and Multi-Frame Sync
(2 kHz) clocks are provided on outputs TO10
(FrSync) and TO11 (MFrSync). The FrSync and
MFrSync clocks have a 50:50 mark space ratio.
These are driven from the TOUT0 clock. They are
synchronized with their counterparts in a second
ACS8510 device (if used), using the technique
described later.
Low Jitter Multiple E1/DS1 Outputs
This feature added to Rev2.1 is activated using
the cnfg_control1 register. This sends a fre-
quency of twice the Dig2 rate (see reg addr 39h,
bits 7:6) to the APLL instead of the normal
77.76MHz. For this feature to be used, the Dig2
rate must only be set to 12352kHz/16384kHz
using the cnfg_T0_output_frequencies register.
The normal OC3 rate outputs are then replaced
with E1/DS1 multiple rates. The E1(SONET)/
DS1(SDH) selection is made in the same way as
for Dig2 using the cnfg_T0_output_enable reg-
ister. Table 9 shows the relationship between
primary output frequencies and the correspond-
ing output in E1/DS1 mode, and which output
they are available from.
Revision 2.00/September 2003 Semtech Corp.
16
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