ACS8510 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8510' PDF : 69 Pages View PDF
ACS8510 Rev2.1 SETS
ADVANCED COMMUNICATIONS
Table 12. Register Map Description (continued).
Addr. Parameter Name
(Hex)
cnfg_ref_source_frequency
2B (continued)
Description
Frequency of reference source <I_12>
FINAL
Default
Value (bin)
00000001
2C
Frequency of reference source <I_13>
00000001
2D
Frequency of reference source <I_14>
cnfg_sts_remote_sources_
valid
This register holds the status of the reference sources supplied to the other device in a
master/slave configuration. It is a copy of the other device's sts_sources_valid register. The
register is part of the protection mechanism.
30
Bits (7:0) Reference sources <I_8>:<I_1>
00000001
11111111
31
cnfg_operating_mode
32
cnfg_ref_selection
33
cnfg_mode
34
Bits (7:6) Unused
Bits (5:0) Reference sources <I_14>:<I_9>
This register is used to force the device into a desired operating state, represented by the
binary values shown in Figure 11. Value 0 (hex) allows the control state machine to operate
automatically.
Bits (7:3) Unused
Bits (2:0) Desired operating state (as per Figure 11)
This register is used to force the device to select a particular input reference source,
irrespective of its priority. Writing to this register temporarily raises the selected input to
priority '1'. Provided no other input is already programmed with priority '1', and revertive mode
is on, this source will be selected.
Bits (7:4) Unused
XX111111
XXXXX000
XXXX1111
Bits (3:0) Desired reference source (0000 and 1111 disables the force selection, and
allows automatic selection of all sources, default is 1111)
This register contains several individual configuration fields, as detailed below:
Bit 7
=1 Auto 2 kHz Sync enable: External 2 kHz Sync will be enabled only when the source is
locked to 6.48 MHz. Otherwise it will be disabled (default)
=0 Auto 2 kHz Sync disable: The user controls this function using bit 3 of this register, as
described below
Bit 6
=1 Phase Alarm Timeout enable: The phase alarm will timeout after 100 seconds (default)
=0 Phase Alarm Timeout disable: The phase alarm will not timeout and must be reset by
software
Bit 5
=1 Rising Clock Edge selected: The device will reference to the rising edge of the external
12.8 MHz crystal oscillator signal
=0 Falling edge Edge selected: The device will reference to the falling edge of the external
12.8 MHz crystal oscillator signal (default)
Bit 4
=1 Holdover offset enable: The device will adopt the Holdover offset value stored in the
cnfg_holdover_offset register, in order to set the frequency in Holdover
=0 Holdover offset disable: The device will ignore the value and Holdover will freeze the
frequency of the DPLL on entering Holdover mode (default)
11001000
(MSTSLVB=0)
(SONSDHB=0)
11001100
(MSTSLVB=0)
(SONSDHB=1)
11000010
(MSTSLVB=1)
(SONSDHB=0)
11000110
(MSTSLVB=1)
(SONSDHB=1)
Bit 3
= 1 External 2 kHz Sync Enable: The device will align the phase of its internally generated
Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) with that of the signal
supplied to the Sync2K pin. The device should be locked to a 6.48 MHz output from another
ACS8510.
= 0 External 2 kHz Sync Disable: The device will ignore the Sync2k pin.
Revision 2.00/September 2003 Semtech Corp.
31
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