ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
DivN Mode
DivN mode allows the input to be divided by any integer
value. The mode is engaged by bit 7 of registers 22 to 2D
allowing any input to use this mode. The divide value is set
by register 46 & 47, it must be set so that the frequency
after division is 8 kHz.
The DivN function is defined as :
DivN = "Divide by (N+1)", i.e. it is the dividing factor used
for the division of the input frequency, and has a value of
(N+1) where N is an integer from 1 to 12499 inclusive, as
set by registers 46 & 47h.
Therefore, in DivN mode the input frequency can be
divided by any integer value between 2 to 12500.
Consequently, any input frequency which is a multiple of 8
kHz, between 8 kHz to 100 MHz, can be supported by
using DivN mode.
Any reference input can be set to use DivN independently
of the frequencies and configurations of the other inputs.
However only one value of N is allowed, so all inputs with
DivN selected must be running at the same frequency.
DivN Examples
(a) To lock to 2.000 MHz:
(i) Set the cnfg_ref_source_frequency register (address
22 - 2D) to 10XX0000 (binary) to enable DivN, and
set the frequency to 8 kHz - the frequency required
after division. (XX = "Leaky Bucket" ID for this input).
(ii) To achieve 8 kHz, the 2 MHz input must be divided by
250. So, if DivN=250 = (N + 1) then N must be set to
249. This is done by writing F9 hex (249 decimal) to
the DivN register pair at address 46 & 47.
(b) To lock to 10.000 MHz:
(i) The cnfg_ref_source_frequency register (address 22 -
2D) is set to 10XX0000 (binary) to set the DivN and
the frequency to 8 kHz, the post-division frequency.
(XX = "Leaky Bucket" ID for this input).
(ii) To achieve 8 kHz, the 10 MHz input must be divided
by 1,250. So, if DivN, = 250 = (N+1) then N must be
set to 1,249. This is done by writing 4E1 hex (1,249
decimal) to the DivN register pair at address 46 & 47.
Direct Lock Mode 155 MHz.
The max frequency allowed for phase comparison is 77.76
MHz, so for the special case of a 155 MHz input set to
Direct Lock Mode, there is a divide-by-two function
automatically selected to bring the frequency down to
within the limits of operation.
PECL/LVDS/AMI Input Port Selection
The choice of PECL or LVDS compatibility is programmed
via the cnfg_differential_inputs register, address 36h.
Unused PECL differential inputs should be fixed with one
input High (VDD) and the other input Low (GND), or set in
LVDS mode and left floating, in which case one input is
internally pulled High and the other Low .
An AMI port supports a composite clock, consisting of a 64
kHz AMI clock with 8 kHz boundaries marked by deliberate
violations of the AMI coding rules, as specified in ITU
recommendation G.703[6]. Departures from the nominal
pattern are detected within the ACS8514, and may cause
reference-switching if too frequent. See section DC
Characteristics: AMI Input/Output Port, for more details. If
the AMI port is unused, the pins (I1 and I2) should be tied
to GND.
Table 5 Input Reference Source Selection and Priority Table for T4 DPLL
Port
Number
I1
I2
I3
I4
I5
Channel
Number (Bin)
Input Port
Technology
0001
AMI
0010
AMI
0011
TTL/CMOS
0100
TTL/CMOS
0101
LVDS/PECL
LVDS default
Frequencies Supported
64/8 kHz (composite clock, 64 kHz + 8 kHz)
Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz
64/8 kHz (composite clock, 64 kHz + 8 kHz)
Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz
Up to 100 MHz (see Note 0)
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 100 MHz (see Note 0)
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 155.52 MHz (see Note (ii))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Default
Priority
0
0
0
0
6
Revision 3.00 April 2007 © Semtech Corp.
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