ACS8515LC View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8515LC' PDF : 50 Pages View PDF
ACS8515 Rev2.1 LC/P
ADVANCED COMMUNICATIONS
FINAL
Table 11. Register Map Description (continued).
Addr. Parameter Name
(Hex)
Description
cnfg_nominal_frequency
This register holds a 16 bit unsigned integer allowing compensation for offset of the crystal
oscillator from the nominal 12.8 MHz. See section Crystal Frequency Calibration. Default
results in 0 ppm adjustment.
3C
Bits (7:0) cnfg_nominal_frequency bits (7:0)
3D
cnfg_holdover_offset
40
cnfg_freq_limit
Bits (7:0) cnfg_nominal_frequency bits (15:8)
This register holds 1 bit which must be set to '0' during initialization.
Bit 7
Must be set to '0' during initialization
Bits (6:0) Unused
This register holds a 10 bit unsigned integer representing the pull-in range of the DPLL. It
should be set according to the accuracy of crystal implemented in the application, using the
following formula;
Default
Value (bin)
10011001
10011001
1XXXXXXX
Frequency range +/- (ppm) = (cnfg_freq_limit x 0.0785)+0.01647 or
cnfg_freq_limit = (Frequency range +/- (ppm) - 0.01647) / 0.0785
41
42
cnfg_interrupt_mask
Default value when SRCSW is left unconnected or tied low is ±9.3 ppm. Default value when
SRCSW is high is the full range of around ±80 ppm.
Bits (7:0) cnfg_freq_limit bits (7:0)
Bits (7:2) Unused
Bits (1:0) cnfg_freq_limits bits (9:8)
Each bit, if set '0' will disable the appropriate interrupt source in the interrupt status register.
Bit (7:6) Must be set to '00' during initialisation
01110110
(SRCSW low)
11111111
(SRCSW high)
XXXXXX00
(SRCSW low)
XXXXXX11
(SRCSW high)
Bit 5 Status SEC2DIFF
Bit 4 Status SEC1DIFF
43
Bit 3 Status SEC2
11111111
Bit 2 Status SEC1
Bit (1:0) Must be set to '00' during initialisation
Bit 7 Oper. mode
Bit 6 Main ref
44
Bit (5:1) Must be set to '00000' during initialisation
11111111
45
cnfg_freq_divn
Bit 0 Interrupt source
Bit (7:5) Unused
Bit (4:0) Must be set to '00000' during initialisation
This 14 bit integer is used as the divisor for any input to get the phase locking frequency
desired. Only active for inputs with the DivN bit set to ‘1’. This will cause the input frequency
to be divided by (n+1) prior to phase comparison, e.g. program N to:
XXX11111
((input freq)/8kHz)-1
The reference_source_frequency bits should be set to reflect the closest spot frequency to the
input frequency, but must be lower than the input frequency.
46
Bits (7:0) cnfg_freq_divn bits (7:0)
00000000
Bits (7:6) Unused
47
Bits (5:0) cnfg_freq_divn bits (13:8)
XX000000
Revision 2.01/December 2005 Semtech Corp.
27
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