ACS8522 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522' PDF : 118 Pages View PDF
ACS8522 SETS LITE
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
programmable for all PLL parameters of bandwidth (from T4 DPLL Main Features
0.1 Hz up to 70 Hz), damping factor (from 1.2 to 20),
frequency acceptance and output range (from 0 to
80 ppm, typically 9.2 ppm), input frequency (12 common
SONET/SDH spot frequencies) and input-to-output phase
offset (in 6 ps steps up to 200 ns). There is no
requirement to understand the loop filter equations or
detailed gain parameters since all high level factors such
as overall bandwidth can be set directly via registers in
the microprocessor interface. No external critical
components are required for either the internal DPLLs or
z Single programmable DPLL bandwidth control: 18 Hz,
35 Hz or 70 Hz
z Programmable damping factor: For optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
z Multiple phase lock detectors
z Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
APLLs, providing another key advantage over traditional z DS3/E3 support (44.736 MHz / 34.368 MHz) at same
discrete designs.
time as OC-N rates from T0 DPLL
The T4 DPLL is similar in structure to the T0 DPLL, but
since the T4 is only providing a clock synthesis and input
to output frequency translation function, with no defined
requirement for jitter attenuation or input phase jump
absorption, then its bandwidth is limited to the high end
and the T4 does not incorporate many of the Phase Build-
z Low jitter E1/DS1 options at same time as OC-N rates
from T0 DPLL
z Frequencies of n x E1/DS1 including 16 and 12 x E1,
and 16 and 24 x DS1 supported
z Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs
z Can use the T4 DPLL as an Independent FrSync DPLL
out and adjustment facilities of the T0 DPLL.
z Can use the phase detector in T4 DPLL to measure
the input phase difference between two inputs.
TO DPLL Main Features
z Two programmable DPLL bandwidth controls (Locked
and Acquisition bandwidth), each with 10 steps from
0.1 Hz to 70 Hz
The structure of the T0 and T4 PLLs are shown later in
Figure 10 in the section on output clock ports. That
section also details how the DPLLs and particular output
frequencies are configured. The following sections detail
some component parts of the DPLL.
z Programmable damping factor: For optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
z Multiple phase lock detectors
z Input to output phase offset adjustment
(Master/Slave), ±200 ns, 6 ps resolution step size
z PBO phase offset on source switching - disturbance
down to ±5 ns
TO DPLL Automatic Bandwidth Controls
In Automatic Bandwidth Selection mode (Reg. 3B), the T0
DPLL bandwidth setting is selected automatically from
the Acquisition Bandwidth or Locked Bandwidth
configurations programmed in cnfg_T0_DPLL_acq_bw
Reg. 69 and cnfg_T0_DPLL_locked_bw Reg. 67
respectively. If this mode is not selected, the DPLL
acquires and locks using only the bandwidth set by
Reg. 67.
z Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
z Holdover frequency averaging with a choice of:
Average times: 8 minutes or 110 minutes. Value can
also be read out.
z Multiple E1 and DS1 outputs supported
z Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs.
Phase Detectors
A Phase and Frequency detector is used to compare input
and feedback clocks. This operates at input frequencies
up to 77.76 MHz. The whole DPLL can operate at spot
frequencies from 2 kHz up to 77.76 MHz. A common
arrangement however is to use Lock8k mode (see Bit 6 of
Reg. 22, 23, 27 and 28) where all input frequencies are
divided down to 8 kHz internally. Marginally better MTIE
figures may be possible in direct lock mode due to more
regular phase updates.
Revision 5/November 2006 © Semtech Corp.
Page 18
www.semtech.com
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