ACS8522A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522A' PDF : 118 Pages View PDF
ACS8522A SETS LITE
ADVANCED COMMS & SENSING
Address (hex): 79 (cont...)
FINAL
Register Name cnfg_phase_alarm_timeout
Description
(RO) Register to configure how
long before a phase alarm is
raised on an input
DATASHEET
Default Value 0011 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
timeout_value
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[5:0]
timeout_value
Phase alarms can only be raised on an input when
the T0 DPLL is attempting to lock to it. Once an
input has been rejected due to a phase alarm, there
is no way to measure whether it is good again,
because it is no longer selected by the DPLL. The
phase alarms can either remain until reset by
software, or timeout after 128 second, as selected
in Reg. 34 Bit 6, phalarm_timeout
-
This 6-bit unsigned integer represents the length of
time before a phase alarm will be raised on an
input. The value multiplied by 2 gives the time in
seconds. This time value is the time that the
controlling state machine will spend in Pre-locked,
Pre-locked2 or Phase-lost modes before setting the
phase alarm on the selected input.
Address (hex): 7A
Register Name cnfg_sync_pulses
Description
(R/W) Register to configure the
Sync outputs, and select the
source for the 2 kHz and 8 kHz
outputs from O1 to O4.
Default Value 0000 0000
Bit 7
2k_8k_from_T4
Bit 6
Bit 5
Bit 4
Bit 3
8k_invert
Bit 2
8k_pulse
Bit 1
2k_invert
Bit 0
2k_pulse
Bit No.
Description
Bit Value Value Description
7
[6:4]
3
2
1
2k_8k_from_T4
Register to select the source (T0 or T4) for the 2 kHz
and 8 kHz outputs available from O1 to O4.
Not used.
8k_invert
Register bit to invert the 8 kHz output from FrSync.
8k_pulse
Register bit to enable the 8 kHz output from FrSync
to be either pulsed or 50:50 duty cycle. Output 03
must be enabled to use “pulsed output” mode on
the FrSync output, and then the pulse width on the
FrSync output will be equal to the period of the
output programmed on O3.
2k_invert
Register bit to invert the 2 kHz output from
MFrSync.
0
2/8 kHz on O1 to O4 generated from the T0 DPLL.
1
2/8 kHz on O1 to O4 generated from the T4 DPLL.
-
-
0
8 kHz FrSync output not inverted.
1
8 kHz FrSync output inverted.
0
8 kHz FrSync output not pulsed.
1
8 kHz FrSync output pulsed.
0
2 kHz MFrSync output not inverted.
1
2 kHz MFrSync output inverted.
Revision 1.00/September 2007 © Semtech Corp.
Page 101
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