ACS8522A View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8522A' PDF : 118 Pages View PDF
ACS8522A SETS LITE
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Bits 3:0, or changed via the T4 priority (Reg. 19 to 1C, MFrSync and 8 kHz FrSync outputs keep their precise
when Reg. 4B, Bit 4 = 1).
alignment with the other output clocks.
Consequently the phase detector from the T4 DPLL could
be used to measure the phase difference between the
currently selected source and the stand-by source, or it
could be used to measure the phase wander of all stand-
by sources with respect to the current source by selecting
each input in sequence. An MTIE and TDEV calculation
could be made for each input via external processing.
MFrSync and FrSync Alignment-SYNC2K
The SYNC2K input will normally be a 2 kHz frequency and
only its falling edge is used. It can however be at a
frequencies of 4 kHz or 8 kHz without any change to the
register setups. Only alignment of the 8 kHz will be
achieved in this case.
Safe sampling of the SYNC2K input is achieved by using
the currently selected clock reference source to do the
input sampling. This is based on the principle that FrSync
alignment is being used on a Slave device that is locked
to the clock reference of a Master device that is also
providing the 2 kHz SYNC2K input. Phase Build-out mode
should be off (Reg. 48, Bit 2 = 0). The 2 kHz MFrSync
output from the Master device has its falling edge aligned
with the falling edge of the other output clocks, hence the
SYNC2K input is normally sampled on the rising edge of
the current input reference clock, in order to provide the
most margin. Some modification of the expected timing of
the SYNC2K with respect to the reference clock can be
achieved via Reg. 7B, Bits [1:0]. This allows for the
SYNC2K input to arrive either half a reference clock cycle
early or up to one and a half cycle late, hence allowing a
safe sampling margin to be maintained.
A different sampling resolution is used depending on the
input reference frequency and the setting of Reg. 7B,
cnfg_sync_phase, Bit 6 indep_FrSync/MFrSync. With this
bit Low, the SYNC2K input sampling has a 6.48 MHz
resolution, this being the preferred reference frequency to
lock to from the Master, in conjunction with the SYNC2K
2 kHz, since it gives the most timing margin on the
sampling and aligns all of the higher rate OC-3 derived
clocks. When Bit 6 is High the SYNC2K can have a
sampling resolution of either 19.44 MHz (when the
current locked to reference is 19.44 MHz) or 38.88 MHz
(all other frequencies). This would allow for instance a
19.44 MHz and 2 kHz pair to be used for Slave
synchronization or for Line card synchronization. Reg. 7B
Bit 7, indep_FrSync/MFrSync controls whether the 2 kHz
When indep_FrSync/MFrSync Reg. 7B Bit 7 is Low the
FrSyncs and the other higher rate clocks are not
independent and their alignment on the falling 8kHz edge
is maintained. This means that when Bit Sync_OC-N_rates
is High, the OC-N rate dividers and clocks are also
synchronized by the SYNC2K input. On a change of phase
position of the SYNC2K, this could result in a shift in
phase of the 6.48 MHz output clock when a 19.44 MHz
precision is used for the SYNC2K input. To avoid
disturbing any of the output clocks and only align the
MFrSync and FrSync outputs, at the chosen level of
precision, then independent Frame Sync mode can be
used (Reg. 7B, bit 7 = 1). Edge alignment of the FrSync
output with other clocks outputs may then change
depending on the SYNC2K sampling precision used. For
example with a 19.44 MHz reference input clock and
Reg. 7B, bits 6 & 7 both High (independent mode and
Sync OC-N rates), then the FrSync output will still align
with the 19.44 MHz output but not with the 6.48 MHz
output clock.
The FrSync and MFrSync outputs always come from the
T0 DPLL path. 2kHz and 8kHz outputs can also be
produced at the O1 to O4 outputs. These can come from
either the T0 DPLL or from the T4 DPLL, controlled by
Reg. 7A, bit 7.
If required, this allows the T4 DPLL to be used as a
separate PLL for the FrSync and MFrSync path with a
2 kHz input and 2 kHz and 8 kHz Frame Sync outputs.
Output Clock Ports
The device supports a set of main output clocks, O1 to O4
and a pair of secondary Sync outputs, FrSync and
MFrSync. The four main output clocks are independent of
each other and are individually selectable. The two
secondary output clocks, FrSync and MFrSync, are
derived from the T0 path only. The frequencies of the
main output clocks are selectable from a range of pre-
defined spot frequencies, as defined in Table 11. Output
technologies are TTL/CMOS for all outputs except O1
which can be PECL or LVDS.
PECL/LVDS Output Port Selection
The choice of PECL or LVDS compatibility for Output O1 is
programmed via the cnfg_differential_outputs register,
Reg. 3A.
Revision 1.00/September 2007 © Semtech Corp.
Page 27
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