ACS8526T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526T' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Table 11 APLL1 Frequencies
FINAL
APLL1 Frequency
Synthesis/MUX setting for APLL1
input
DPLL1 Frequency Control
Reg. 65 Bits[2:0]
311.04
Normal (digital feedback)
000
311.04 MHz
Normal (analog feedback)
001
98.304 MHz
12E1 (digital feedback)
010
131.072 MHz
16E1 (digital feedback)
011
148.224 MHz
24DS1 (digital feedback)
100
98.816 MHz
16DS1 (digital feedback)
101
-
Do not use
110
-
Do not use
111
DATASHEET
Output Jitter Level
ns (p-p)
<0.5
<0.5
<2
<2
<2
<2
-
-
Table 12 APLL2 Frequencies
APLL2
Frequency
DPLL Mode DPLL2 Forward DFS
Frequency (MHz)
311.04 MHz
DPLL2-Squelch 77.76
ed
311.04 MHz DPLL2-Normal 77.76
98.304 MHz DPLL2-12E1 24.576
131.072 MHz DPLL2-16E1 32.768
148.224 MHz DPLL2-24DS1 37.056 (2*18.528)
98.816 MHz DPLL2-16DS1 24.704
274.944 MHz DPLL2-E3
68.736 (2*34.368)
178.944 MHz DPLL2-DS3 44.736
98.304 MHz DPLL1-12E1
-
131.072 MHz DPLL1-16E1
-
148.224 MHz DPLL1-24DS1
-
98.816 MHz DPLL1-16DS1
-
DPLL2 Freq Control
Register Bits
Reg. 64 Bits [2:0]
APLL2 Input from
DPLL1 or 2.
Reg. 65 Bit 6
000
0 (DPLL2 selected)
001
0 (DPLL2 selected)
010
0 (DPLL2 selected)
011
0 (DPLL2 selected)
100
0 (DPLL2 selected)
101
0 (DPLL2 selected)
110
0 (DPLL2 selected)
111
0 (DPLL2 selected)
XXX
1 (DPLL1 selected)
XXX
1 (DPLL1 selected)
XXX
1 (DPLL1 selected)
XXX
1 (DPLL1 selected)
DPLL1 + Synthesis
Freq to APLL2
Register Bits
Reg. 65 Bits [5:4]
Output
Jitter Level
ns (p-p)
XX
<0.5
XX
<0.5
XX
<0.5
XX
<0.5
XX
<0.5
XX
<0.5
XX
<0.5
XX
<0.5
00
<2
01
<2
10
<2
11
<2
Note...If using Synthesis for inputs to both APLL1 and APLL2, then they must both use the same synthesis settings.
Revision 4.01/June 2006 © Semtech Corp.
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