ACS8526T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526T' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 61
Register Name cnfg_output_frequency
(Output O2)
FINAL
DATASHEET
Description
(R/W) Register to configure and
enable the frequencies available
on Output O2.
Default Value 0000 XXXX
Where XXXX is set by values on
Pins O2_FREQ[2:0], SONSDHB
and O1_FREQ[2:0]. See Note in
[3:0] description.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
output_freq_O2
Bit 0
Bit No.
Description
Bit Value Value Description
[7:4]
[3:0]
Not used.
output_freq_O2
Configuration of the output frequency available at
Output O2. Many of the frequencies available are
dependent on the frequencies of the APLL1 and the
APLL2. These are configured in Reg. 64 and
Reg. 65. See “Output Frequency Selection by
Register Programming” on page 17.
Note...The values on the pins O2_FREQ [2:0],
SONSDHB and 01_FREQ[2:0] determine the default
output frequency for Output O2, which, at power-
up/reset is written to the cnfg_output_frequency
register. The value in this register can, after the
initialization period (251 ms after PORB goes High),
be changed by writing to it via the serial interface,
however any subsequent reset will cause this
register’s value to be overwritten by whatever value
is on the pins at the time of the reset. See “Output
Frequency Selection by Hardware” and Table 7 on
page 18.
-
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-
Output disabled.
2 kHz.
8 kHz.
Digital2 (Reg. 39 cnfg_digital_frequencies).
Digital1 (Reg. 39 cnfg_digital_frequencies).
APLL1 frequency/48.
APLL1 frequency/16.
APLL1 frequency/12.
APLL1 frequency/8.
APLL1 frequency/6.
APLL1 frequency/4.
APLL2 frequency/64.
APLL2 frequency/48.
APLL2 frequency/16.
APLL2 frequency/8.
APLL2 frequency/4.
Revision 4.01/June 2006 © Semtech Corp.
Page 46
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