ACS8530T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8530T' PDF : 152 Pages View PDF
ACS8530 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
the coarse phase detector range, since these functions go
hand in hand. This detector may be used in the case
where it is required that a phase loss indication is not
given for reasonable amounts of input jitter and so the
fine phase loss detector is disabled and the coarse
detector is used instead.
Damping Factor Programmability
The DPLL damping factor is set by default to provide a
maximum wander gain peak of around 0.1 dB. Many of
the specifications (e.g. GR-1244-CORE[19], G.812[10] and
G.813[11]) specify a wander transfer gain of less than
0.2 dB. GR-253[17] specifies jitter (not wander) transfer of
less than 0.1 dB. To accommodate the required levels of
transfer gain, the ACS8530 provides a choice of damping
factors, with more choice given as the bandwidth setting
increases into the frequency regions classified as jitter.
Table 5 shows which damping factors are available for
Local Oscillator Clock
The Master system clock on the ACS8530 should be
provided by an external clock oscillator of frequency
12.800 MHz. The clock specification is important for
meeting the AT&T, ITU/ETSI and Telcordia performance
requirements for Holdover mode. Telcordia specifications
require a non-temperature-related drift of less than 1 ppb
per day and a drift of 10 ppb over the temperature range
0 to +50°C.
Telcordia GR-1244 Specification
Table 6 Stratum 3E Specification
Parameter
Initial Offset
Offset Over Temperature (Note i)
Drift Rate Due to Ageing
Value
±1 x 10-9
±10 x 10-9 (Note ii)
±1.16 x 10-14/second (Note ii)
(= 1 x 10-9/day)
selection at the different bandwidth settings, and what
the corresponding jitter transfer approximate gain peak
will be.
Table 5 Available Damping Factors for different DPLL
Bandwidths, and associated Jitter Peak Values
Notes: (i) Figure quoted is for long-term drift over the range
0°C to +40°C, but for short-term (<96 hours) the range is
-5°C to +50°C.
Max rate of drift = ±30°C/hr.
(ii) Determined by external XO
Bandwidth
Reg. 6B [2:0] Damping Gain Peak/ dB Please contact Semtech for information on crystal
Factor selected
oscillator suppliers.
0.5 mHz to 4 Hz 1, 2, 3, 4, 5 5
0.1
Crystal Frequency Calibration
8 Hz
1
2.5
0.2
The absolute crystal frequency accuracy is less important
2, 3, 4, 5
5
0.1
than the stability since any frequency offset can be
compensated by adjustment of register values in the IC.
18 Hz
1
1.2
0.4
This allows for calibration and compensation of any
2
2.5
0.2
3, 4, 5
5
0.1
crystal frequency variation away from its nominal value.
± 50 ppm adjustment would be sufficient to cope with
most crystals, in fact the range is an order of magnitude
35 Hz
1
2
1.2
0.4
2.5
0.2
larger due to the use of two 8-bit register locations. The
setting of the cnfg_nominal_frequency register allows for
this adjustment. An increase in the register value
3
5
0.1
increases the output frequencies by 0.0196229 ppm for
each LSB step.
4, 5
10
0.06
70 Hz
1
1.2
0.4
Note...The default register value (in decimal) = 39321
(9999 hex) = 0 ppm offset. The minimum to maximum offset
2
2.5
0.2
range of the register is 0 to 65535 dec, giving an adjustment
range of -771 ppm to +514 ppm of the output frequencies, in
3
5
0.1
0.0196229 ppm steps. Example: If the crystal was oscillating
at 12.8 MHz + 5 ppm, then the calibration value in the register
4
10
0.06
to give a - 5 ppm adjustment in output frequencies to
compensate for the crystal inaccuracy, would be:
5
20
0.03
39321 - (5 / 0.0196229) = 39066 (dec) = 989A (hex).
Revision 3.02/November 2005 © Semtech Corp.
Page 22
www.semtech.com
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