ACT8712QLCHA-T View Datasheet(PDF) - Active-Semi, Inc
Part Name
Description
MFG CO.
ACT8712QLCHA-T
Active-Semi, Inc
'ACT8712QLCHA-T' PDF : 36 Pages View PDF
ACT8712
Rev0, 25-Feb-08
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTION
General Description
The ACT8712 offers an array of system manage-
ment functions that allow it to provide optimal per-
formance in a wide range of applications.
I2C Serial Interface
At the core of the ACT8712’s flexible architecture is
an I2C interface that permits optional programming
capability to enhance overall system performance.
To ensure compatibility with a wide range of system
processors, the ACT8712 uses standard I2C com-
mands; I2C write-byte commands are used to pro-
gram the ACT8712, and I2C read-byte commands
are used to read the ACT8712’s internal registers.
The ACT8712 always operates as a slave device,
and is addressed using a 7-bit slave address fol-
lowed by an eighth bit, which indicates whether the
transaction is a read-operation or a write-operation,
[1010 011x].
SDA is a bi-directional data line and SCL is a clock
input. The master initiates a transaction by issuing a
START condition, defined by SDA transitioning from
high to low while SCL is high. Data is transferred in
8-bit packets, beginning with the MSB, and is
clocked-in on the rising edge of SCL. Each packet
of data is followed by an “Acknowledge” (ACK) bit,
used to confirm that the data was transmitted suc-
cessfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com
System Startup and Shutdown
The ACT8712 features a flexible control architec-
ture that supports a variety of software-controlled
enable/disable functions that make it a simple yet
flexible and highly configurable solution.
The ACT8712 is automatically enabled when any of
the following conditions exists:
1) A valid supply voltage is present at VIN,
2) nMSTR is asserted low, or
3) ON1 is asserted high.
If any of these conditions is true, the ACT8712 en-
ables REG1 and REG2, powering up the system
processor so that the startup and shutdown se-
quences may be controlled via software. Each of
these startup conditions are described in detail below.
Automatic Enable Due to Valid VIN Supply
The ACT8712 battery charger and step-down
DC/DC converters (REG1 and REG2) are automati-
cally enabled when a valid input supply is applied to
VIN. Automatically enabling these functions simpli-
fies system design and eliminates the need for ex-
ternal input supply-detection circuitry.
Manual Enable Due to Asserting nMSTR Low
System startup is initiated when the user presses
the push-button, asserting nMSTR low. When this
occurs, both REG1 and REG2 are enabled and
nRSTO is asserted low to hold the microprocessor
in RESET for 260ms. nRSTO goes high-Z upon
expiration of the reset timer, de-asserting the proc-
essor’s reset input and allowing the microprocessor
to initiate its power up sequence. Once the power-
up routine is successfully completed, the microproc-
essor must assert ON1 so that the ACT8712 re-
mains enabled after the push-button is released by
the user. Upon completion of the start-up sequence
the processor assumes control of the power system
and all further operation is software-controlled.
Manual Enable Due to Asserting ON1 High
The ACT8712 is compatible with applications that
do not utilize it’s push-button control function, and
may be enabled by simply driving ON1 to a logic-
high. In this case, the signal driving ON1 controls
enable/disable timing, although software-controlled
enable/disable sequences are still supported if the
processor assumes control of the power system
once the startup sequence is completed.
Shutdown Sequence
Once a successful power-up routine is completed,
the system processor controls the operation of the
power system, including the system shutdown tim-
ing and sequence. The ACT8712 asserts nIRQ low
when nMSTR is asserted low, providing a simple
means of alerting the system processor when the
user wishes to shut the system down. Asserting
nIRQ interrupts the system processor, initiating an
interrupt service routine in the processor which will
reveal that the user pressed the push-button. The
microprocessor may validate the input, such as by
ensuring that the push-button is asserted for a mini-
mum amount of time, then initiates a software-
controlled power-down routine, the final step of
which is to de-assert the ON1 input, disabling
REG1 and REG2 and shutting the system down.
Innovative Products. Active Solutions.
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of Philips Electronics.
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www.active-semi.com
Copyright © 2008 Active-Semi, Inc.
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