AD120 View Datasheet(PDF) - AMIC Technology
Part Name
Description
MFG CO.
'AD120' PDF : 13 Pages View PDF
AD120
Input/Output Pin Function
Pin No.
11
7
8
9
6
4,5,
13,14
18 - 275
12
10
3, 15
1, 17
2, 16
Symbol
CP
R /L
XON
XOFF
OGW
ST1, ST2,
ST1X, ST2X
OUT0~
OUT257
VSS
VDD
VH
VL
VOFF
I/O
Description
I Clock pulse
I Right / left direction control for shift register
When R /L is LOW, data are shifted to the right, or ST1 / ST2 output0 output1
.… output257.
When R /L is HIGH, data are shifted to the left, or ST1X / ST2X output257
output256 .... output0.
I XON to force all the outputs to VH voltage.
It is not synchronous to CP.
I XOFF to force all the outputs to VOFF voltage.
It is not synchronous to CP.
I Output Gate pulse Width to select output_waveform format.
I/O When R /L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined
as outputs .
The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses.
When R /L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined
as outputs.
The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses.
O
PWR
PWR
PWR
Output drivers
These outputs are synchronized to CP pulses.
The output format and voltage level are controlled by OGW, XON, XOFF , ST1 /
ST2, ST1X / ST2X and R /L correspondingly as shown in the diagram.
Reference voltage
Supply voltage for logic operation
VDD and VSS are voltage levels of input / output logic signals
High voltage for output drivers
PWR Low voltage for output drivers
PWR OFF voltage for output drivers
PRELIMINARY (August, 2001, Version 0.0)
3
AMIC Technology, Inc
Share Link: 
