AD532KD+ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD532KD+' PDF : 7 Pages View PDF
ORDERING GUIDE
Model
Temperature
Ranges
AD532JD
0°C to +70°C
AD532JD/+
0°C to +70°C
AD532KD
0°C to +70°C
AD532KD/+
0°C to +70°C
AD532JH
0°C to +70°C
AD532KH
0°C to +70°C
AD532J Chip
0°C to +70°C
AD532SD
–55°C to +125°C
AD532SD/883B
–55°C to +125°C
JM38510/13903BCA –55°C to +125°C
AD532SE/883B
–55°C to +125°C
AD532SH
–55°C to +125°C
AD532SH/883B
–55°C to +125°C
JM38510/13903BIA –55°C to +125°C
AD532S Chip
–55°C to +125°C
Package
Descriptions
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Header
Header
Chip
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
LCC
Header
Header
Header
Chip
Package
Options
D-14
D-14
D-14
D-14
H-10A
H-10A
D-14
D-14
D-14
E-20A
H-10A
H-10A
H-10A
AD532
CHIP DIMENSIONS AND BONDING DIAGRAM
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure
1, and the complete schematic in Figure 2. In the multiplying
and squaring modes, Z is connected to the output to close the
feedback around the output op amp. (In the divide mode, it is
used as an input terminal.)
The X and Y inputs are fed to high impedance differential am-
plifiers featuring low distortion and good common-mode rejec-
tion. The amplifier voltage offsets are actively laser trimmed
to zero during production. The product of the two inputs is
resolved in the multiplier cell using Gilbert’s linearized trans-
conductance technique. The cell is laser trimmed to obtain
VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used
to obtain low output impedance and make possible self-contained
operation. The residual output voltage offset can be zeroed at
VOS in critical applications . . . otherwise the VOS pin should be
grounded.
Figure 1. Functional Block Diagram
REV. B
Figure 2. Schematic Diagram
–3–
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