AD7401AYRWZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD7401AYRWZ' PDF : 20 Pages View PDF
AD7401A
DIGITAL FILTER
The overall system resolution and throughput rate is determined
by the filter selected and the decimation rate used. The higher
the decimation rate, the greater the system accuracy, as illus-
trated in Figure 26. However, there is a tradeoff between accuracy
and throughput rate and, therefore, higher decimation rates
result in lower throughput solutions. Note that for a given
bandwidth requirement, a higher MCLKIN frequency can allow
for higher decimation rates to be used, resulting in higher SNR
performance.
90
SINC3
80
70
SINC2
60
50
40
30
SINC1
20
10
0
1
10
100
1k
DECIMATION RATE
Figure 26. SNR vs. Decimation Rate for Different Filter Types
A sinc3 filter is recommended for use with the AD7401A. This
filter can be implemented on an FPGA or a DSP.
(( )) H(z) =⎜⎜⎝⎛
1 − Z DR
1 − Z −1
⎟⎟⎠⎞ 3
where DR is the decimation rate.
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge, if
preferred.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input mclk1;
input reset;
input mdata1;
filtered*/
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
output [15:0] DATA;
/*filtered op*/
integer location;
integer info_file;
reg [23:0]
ip_data1;
reg [23:0]
acc1;
reg [23:0]
acc2;
reg [23:0]
acc3;
reg [23:0]
acc3_d1;
reg [23:0]
acc3_d2;
reg [23:0]
diff1;
reg [23:0]
diff2;
reg [23:0]
diff3;
reg [23:0]
diff1_d;
reg [23:0]
diff2_d;
reg [15:0]
DATA;
reg [7:0]
word_count;
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
to a -1 for 2's comp */
else
ip_data1 <= 1;
/* change from a 0
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
MCLKIN
IP_DATA1
+
ACC1+
ACC2+
Z
Z
Z
+
+
Figure 27. Accumulator
ACC3+
Rev. 0 | Page 16 of 20
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