AD7490 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD7490' PDF : 24 Pages View PDF
AD7490
SERIAL INTERFACE
Figure 27 shows the detailed timing diagram for serial interfacing
to the AD7490. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7490 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold goes
back into track on the 14th SCLK falling edge, as shown in
Figure 27 at point B, except when the write is to the Shadow
register, in which case the track-and-hold does not return to
track until the rising edge of CS, that is, Point C in Figure 28.
On the 16th SCLK falling edge, the DOUT line goes back into
three-state (assuming the WEAK/TRI bit is set to 0). Sixteen
serial clock cycles are required to perform the conversion
process and to access data from the AD7490. The 12 bits of
conversion data are preceded by the four channel address bits,
Data Sheet
ADD3 to ADD0, identifying which channel the conversion
result corresponds to. CS going low allows the ADD3 address
bit to be read in by the microprocessor or DSP. The remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges, beginning with the second address bit,
ADD2. Thus, the first SCLK falling edge on the serial clock has
the ADD3 address bit provided and also clocks out address bit
ADD2. The final bit in the data transfer is valid on the 16th
falling edge, having being clocked out on the previous (15th)
falling edge.
Writing information to the control register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the
MSB, that is, the WRITE bit, has been set to 1. If the control
register is programmed to use the Shadow register, writing
information to the Shadow register takes place on all 16 SCLK
falling edges in the next serial transfer (see Figure 28). The
Shadow register is updated upon the rising edge of CS, and the
track-and-hold begins to track the first channel selected in the
sequence.
CS
t2
tCONVERT
t6
SCLK
1
2
3
4
5
6
t3
t3b
t4
t7
DOUT
THREE-
STATE ADD3
ADD2
t9
ADD1
ADD0
DB11
FOUR IDENTIFICATION BITS
DB10
t10
DIN
WRITE
SEQ
ADD3
ADD2
ADD1
ADD0
B
13
14
15
16
t5
t11
DB2
DB1
DB0
t8
DONTC DONTC DONTC
Figure 27. Serial Interface Timing Diagram
tQUIET
THREE-
STATE
C
CS
SCLK
DOUT
DIN
t2
t6 tCONVERT
1
2
3
4
5
6
t3
THREE-
STATE ADD3
ADD2
t9
VIN0
VIN1
t4
t7
ADD1
ADD0
DB11
DB10
FOUR IDENTIFICATION BITS
t10
VIN2
VIN3
VIN4
VIN5
13
14
15
16
DB2
t5
DB1
t11
DB0
t8
VIN13
VIN14
VIN15
THREE-
STATE
Figure 28. Writing to Shadow Register Timing Diagram
Rev. D | Page 22 of 28
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