AD7760 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD7760' PDF : 22 Pages View PDF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DGND 1
MCLKGND 2
MCLK 3
AVDD2 4
AGND2 5
AVDD1 6
AGND1 7
DECAPA 8
REFGND 9
VREF+ 10
AGND4 11
AVDD4 12
AGND2 13
AVDD2 14
AVDD2 15
AGND2 16
PIN 1
48 DB12
47 DB13
46 DB14
45 DB15
44 VDRIVE
43 DGND
AD7760
TOP VIEW
(Not to Scale)
42 DGND
41 DVDD
40 CS
39 RD/WR
38 DRDY
37 RESET
36 SYNC
35 DGND
34 AGND1
33 AVDD1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD7760
Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
6, 33
AVDD1
2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 (Pin 7 and Pin 34, respectively)
with 100 nF and 10 µF capacitors on each pin. See the Decoupling and Layout Recommendations section
for details.
4, 14, 15, 27
AVDD2
5 V Power Supply. These pins should be decoupled to AGND2 (Pin 5 and Pin 13, with 100 nF capacitors
on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the
Decoupling and Layout Recommendations section for details.
24
AVDD3
3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to AGND3 (Pin 23) with a
100 nF capacitor. See the Decoupling and Layout Recommendations section for details.
12
AVDD4
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to Pin 9 with a 10 nF capacitor
in series with a 10 Ω resistor.
7, 34
AGND1
Power Supply Ground for Analog Circuitry Powered by AVDD1.
5, 13, 16, 18, 28 AGND2
Power Supply Ground for Analog Circuitry Powered by AVDD2.
23, 29, 31, 32 AGND3
Power Supply Ground for Analog Circuitry Powered by AVDD3.
11
AGND4
Power Supply Ground for Analog Circuitry Powered by AVDD4.
9
REFGND
Reference Ground. Ground connection for the reference voltage.
41
DVDD
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a 100 nF
capacitor.
44, 63
VDRIVE
Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating
voltage of the logic interface. Both of these pins must be connected together and tied to the same supply.
Each pin should also be decoupled to DGND with a 100 nF capacitor.
1, 35, 42, 43,
53, 62, 64
DGND
Ground Reference for Digital Circuitry.
19
VINA+
Positive Input to Differential Amplifier.
20
VINA−
Negative Input to Differential Amplifier.
21
VOUTA−
Negative Output from Differential Amplifier.
22
VOUTA+
Positive Output from Differential Amplifier.
25
VIN+
Positive Input to the Modulator.
26
VIN−
Negative Input to the Modulator.
10
VREF+
Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4).
See the Reference Voltage Filtering section for more details.
8
DECAPA
Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND.
Rev. A | Page 9 of 36
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