AD7983 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD7983' PDF : 24 Pages View PDF
Data Sheet
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input,
and when it is desired to keep CNV, which is used to sample
the analog input, independent of the signal used to select the
data reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 31, and the
corresponding timing is given in Figure 32.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback (if SDI and CNV are low,
SDO is driven low). Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog
multiplexers, but SDI must be returned low before the
minimum conversion time elapses and then held low for the
maximum conversion time to guarantee the generation of the
busy signal indicator. When the conversion is complete, SDO
goes from high impedance to low.
AD7983
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7983 then enters the acquisition phase
and goes into standby mode. The data bits are clocked out,
MSB first, by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate provided it has an acceptable hold time.
After the optional 17th SCK falling edge or SDI going high,
whichever is earlier, the SDO returns to high impedance.
CNV
SDI AD7983 SDO
CS1
CONVERT
VIO
DIGITAL HOST
47kΩ
DATA IN
SCK
IRQ
CLK
Figure 31. CS Mode, 4-Wire with Busy Indicator Connection Diagram
CNV
ACQUISITION
tCONV
CONVERSION
tCYC
tACQ
ACQUISITION
tSSDICNV
SDI
tHSDICNV
SCK
SDO
tSCKL
tSCK
1
2
3
15
16
17
tHSDO
tSCKH
tDSDO
tDIS
tEN
D15
D14
D1
D0
Figure 32. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Rev. C | Page 21 of 25
Share Link: 
