AD9516-1/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9516-1/PCBZ' PDF : 84 Pages View PDF
AD9516-1
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the
Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section);
however, with these channel dividers, the number of possible
configurations is even more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
• An even DX.Y must be set as MX.Y = NX.Y (low cycles = high
cycles).
• An odd DX.Y must be set as MX.Y = NX.Y + 1 (the number of
low cycles must be one greater than the number of high
cycles).
• If only one divider is bypassed, it must be the second
divider, X.2.
• If only one divider has an even divide by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Divider 3 and Divider 4 are shown in Table 40 through Table 44
Table 40. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
DX.1
NX.1 + MX.1 + 2
DX.2
NX.2 + MX.2 + 2
Output Duty
Cycle
Even
1
1
50%
Odd = 3
1
1
33.3%
Odd = 5
1
1
40%
Even
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Odd
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Even
Even, odd
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Odd
Even, odd
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 41. Divider 3, Divider 4 Duty Cycle; VCO Divider Not
Used; Duty Cycle Correction Off (DCCOFF = 1)
Input Clock
Duty Cycle
DX.1
NX.1 + MX.1 + 2
DX.2
Output
NX.2 + MX.2 + 2 Duty Cycle
50%
1
1
50%
X%
1
1
X%
50%
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
X%
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
50%
Even, odd
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
X%
Even, odd
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Data Sheet
Table 42. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO
Divider Input Duty Cycle = 50%
VCO
DX.1
Divider NX.1 + MX.1 + 2
DX.2
NX.2 + MX.2 + 2
Output
Duty Cycle
Even 1
1
50%
Odd
1
1
50%
Even
Even (NX.1 = MX.1) 1
50%
Odd
Even (NX.1 = MX.1) 1
50%
Even
Odd (MX.1 = NX.1 + 1) 1
50%
Odd
Odd (MX.1 = NX.1 + 1) 1
50%
Even
Even (NX.1 = MX.1) Even (NX.2 = MX.2) 50%
Odd
Even (NX.1 = MX.1) Even (NX.2 = MX.2) 50%
Even
Odd (MX.1 = NX.1 + 1) Even (NX.2 = MX.2) 50%
Odd
Odd (MX.1 = NX.1 + 1) Even (NX.2 = MX.2) 50%
Even
Odd (MX.1 = NX.1 + 1) Odd (MX.2 = NX.2 + 1) 50%
Odd
Odd (MX.1 = NX.1 + 1) Odd (MX.2 = NX.2 + 1) 50%
Table 43. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
DX.1
NX.1 + MX.1 + 2
DX.2
NX.2 + MX.2 + 2
Output
Duty Cycle
Even 1
1
50%
Odd = 3 1
1
(1 + X%)/3
Odd = 5 1
1
(2 + X%)/5
Even
Even
(NX.1 = MX.1)
1
50%
Odd
Even
(NX.1 = MX.1)
1
50%
Even
Odd
(MX.1 = NX.1 + 1)
1
50%
Odd = 3 Odd
(MX.1 = NX.1 + 1)
1
(3NX.1 + 4 + X%)/
(6NX.1 + 9)
Odd = 5 Odd
(MX.1 = NX.1 + 1)
1
(5NX.1 + 7 + X%)/
(10NX.1 + 15)
Even
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Odd
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Even
Odd
Even
(MX.1 = NX.1 + 1) (NX.2 = MX.2)
50%
Odd
Odd
Even
(MX.1 = NX.1 + 1) (NX.2 = MX.2)
50%
Even
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
Odd = 3
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(6NX.1NX.2 + 9NX.1 +
9NX.2 + 13 + X%)/
(3(2NX.1 + 3)
(2NX.2 + 3))
Odd = 5
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(10NX.1NX.2 + 15NX.1 +
15NX.2 + 22 + X%)/
(5(2 NX.1 + 3)
(2 NX.2 + 3))
Rev. C | Page 44 of 80
Share Link: 
