AD9851
J2
BANANA J3
JACKS
J4
+V
5V
GND
AD9851/CGPCB
CLOCK GENERATOR
EVALUATION BOARD
(SSOP PACKAGE)
J7
BNC
TO BYPASS ON BOARD FILTER
1. REMOVE E6 TO E5 JUMPER
2. INSTALL APPROPRIATE R12 FOR IOUT TERMINATION
D3 1 D3
D4 28 D4
D2 2 D2
D1 3 D1
D0 4 D0
U1
AD9851
D5 27 D5
D6 26 D6
D7 25 D7
GND 5 PGND
DGND 24 GND
+V 6 PVCC
DVDD 23 +V
WCLK 7 W CLK
RESET 22 RESET
FQUD 8 FQ UD
IOUT 21
CLKIN 9 REFCLOCK IOUTB 20
10mA
RESET
R1
3.9k
J8
BNC
GND 10 AGND
+V 11 AVDD
12 RSET
13 VOUTN
14 VOUTP
AGND 19 GND
AVDD 18 +V
DACBL 17 NC
VINP 16
VINN 15
J9
BNC
NC = NO CONNECT
R12
E6 E5
R4
100k
R5
100k
R8
100
70MHz ELLIPTICAL LOW-PASS FILTER
7TH ORDER 200 Z
L1
470nH
L2
390nH
L3
390nH
R6
200
C12
1pF
C11
22pF
C14
5.6pF
C13
33pF
C16
4.7pF
C15
22pF
J6
C1
470pF
E1 E2 E4 E3
C17
22pF
R7
200
J1
C36CPR2
U2
1
2
RRSET
3
4
5
6
7
8
9
10
11
74HCT574
9 8D
8 7D
7 6D
6 5D
5 4D
4 3D
3 2D
2 1D
8Q 12
7Q 13
6Q 14
5Q 15
4Q 16
3Q 17
2Q 18
1Q 19
D0
D1
D2
D3
D4
D5
D6
D7
CK OE
12
11 1
13
14 FFQUD
15
16
17
18
STROBE
U3
+V
C6
10F
19
74HCT574
20
21
22
23
24
25
26
27
28
RRESET
WWCLK
FFQUD
RRESET
9 8D
8 7D
7 6D
6 5D
5 4D
4 3D
3 2D
2 1D
8Q 12
7Q 13
6Q 14
5Q 15
4Q 16
RESET
WCLK
FQUD
CHECK
3Q 17
2Q 18
1Q 19
5V
29
CK OE
30
11 1
31 WWCLK
32 CHECK
33
STROBE
34
35
36 STROBE
J5
CLKIN
REMOVE WHEN
USING Y1
R2
50
5V
14
XTAL
OSC
(OPTIONAL)
VCC
Y1
8
OUT
GND
7
5V
C7
10F
C2
0.1F
C3
0.1F
+V
C4
0.1F
C5
0.1F
R9
2.2k
R10
2.2k
R11
2.2k
R3
2.2k
RRESET FFQUD WWCLK STROBE
C8
0.1F
5V
C9
0.1F
C10
0.1F
MOUNTING HOLES
H1 H2 H3 H4
#6 #6 #6 #6
Figure 24. CGPCB Electrical Schematic
REV. D
–21–