AD9910/PCBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9910/PCBZ' PDF : 60 Pages View PDF
AD9910
XTAL_SEL
95
DRV0
CFR3
<31:30>
2
REFCLK_OUT 94
REFCLK
INPUT
SELECT
LOGIC
PLL_LOOP_FILTER
2
PLL ENABLE
CFR3
<8>
REF_CLK 90
ENABLE PLL_LOOP_FILTER
1
0
IN
PLL
OUT 1
0
CHARGE
PUMP DIVIDE
VCO
SELECT
SYSCLK
REF_CLK 91
1
÷2 0
2
ICP
CFR3
<21:19>
7
N
CFR3
<7:1>
3
VCO
CFR3
<26:24>
INPUT DIVIDER
RESETB
CFR3<14>
INPUT DIVIDER BYPASS
CFR3<15>
Figure 30. REF_CLK Block Diagram
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected, the
REF_CLK pins must be driven by an external signal source
(single-ended or differential). Input frequencies up to 2 GHz are
supported. For input frequencies greater than 1 GHz, the input
divider must be enabled for proper operation of the device.
When the PLL is enabled, a buffered clock signal is available at
the REFCLK_OUT pin. This clock signal is the same frequency
as the REF_CLK input. This is especially useful when a crystal
is connected, because it gives the user a replica of the crystal
clock for driving other external devices. The REFCLK_OUT
buffer is controlled by two bits as listed in Table 7.
Table 7. REFCLK_OUT Buffer Control
CFR3<31:30> REFCLK_OUT Buffer
00
Disabled (tristate)
01
Low output current
10
Medium output current
11
High output current
Crystal Driven REF_CLK
When using a crystal at the REF_CLK input, the resonant
frequency should be approximately 25 MHz. Figure 31 shows
the recommended circuit configuration.
39pF
90 REF_CLK
XTAL
39pF
91 REF_CLK
Figure 31. Crystal Connection Diagram
Direct Driven REF_CLK
When driving the REF_CLK inputs directly from a signal
source either single-ended or differential signals can be used.
With a differential signal source, the REF_CLK pins are driven
with complementary signals and ac-coupled with 0.1 μF
capacitors. With a single-ended signal source, either a single-
ended to differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 μF capacitors are used to ac couple both REF_CLK
pins to avoid disturbing the internal dc bias voltage of ~1.35 V.
See Figure 32 for more details.
The REF_CLK input resistance is ~2.5 kΩ differential (~1.2 kΩ
single-ended). Most signal sources have relatively low output
impedances. The REF_CLK input resistance is relatively high,
therefore, its effect on the termination impedance is negligible
and can usually be chosen to be the same as the output
impedance of the signal source. The bottom two examples in
Figure 32 assume a signal source with a 50 Ω output impedance.
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT.
PECL,
LVPECL,
OR
LVDS
DRIVER
0.1µF
90 REF_CLK
TERMINATION
91 REF_CLK
0.1µF
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT.
BALUN
(1:1)
0.1µF
90 REF_CLK
50Ω
91 REF_CLK
0.1µF
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT.
0.1µF
90 REF_CLK
50Ω
91 REF_CLK
0.1µF
Figure 32. Direct Connection Diagram
Phase-Locked Loop (PLL) Multiplier
An internal phase-locked loop (PLL) provides users of the
AD9910 the option to use a reference clock frequency that is
significantly lower than the system clock frequency. The PLL
supports a wide range of programmable frequency multiplica-
tion factors (12× to 127×) as well as a programmable charge
pump current and external loop filter components (connected
via the PLL_LOOP_FILTER pin). These features add an extra
layer of flexibility to the PLL, allowing optimization of phase
noise performance and flexibility in frequency plan develop-
ment. The PLL is also equipped with a PLL_LOCK pin.
The PLL output frequency range (fSYSCLK) is constrained to the
range of 420 MHz ≤ fSYSCLK ≤ 1 GHz by the internal VCO. In
addition, the user must program the VCO to one of six operating
Rev. 0 | Page 24 of 60
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