ADC-305 View Datasheet(PDF) - Murata Power Solutions
Part Name
Description
MFG CO.
'ADC-305' PDF : 6 Pages View PDF
ADC-305
8-Bit, 20MHz CMOS A/D Converters
PARAMETERS
Power Supply Voltage (+AVS, +DVS)
Analog Input Voltage (VIN)
Reference Input Voltage (VRT, VRB)
Digital Input Voltage (VIH, VIL)
Digital Output Voltage (VOH, VOL)
MIN
MAX
–0.5
+7
–0.5 +AVS +0.5
–0.5 +AVS +0.5
–0.5 +DVS +0.5
–0.5 +DVS +0.5
UNITS
Volts
Volts
Volts
Volts
Volts
Functional Specifications
(Specification are typical at TA = +25°C, +VRT = +2.5V, VRB = +0.5V, +AVS = +DVS =
+5v, fS = 20MHz sampling unless otherwise specified.)
Analog Inputs
Input Voltage Range (VIN) ➀
Input Capacitance
(VIN = 1.5Vdc+0.07VRMS)
Input Impedance
Input Signal Bandwidth
(VIN-2Vp-p, –1dB)
Min.
Typ.
Max.
— +0.5 to +2.5 —
—
11
—
—
12.5
—
—
18
—
Units
Volts
pF
kΩ
MHz
REFERENCE INPUTS
Ref. Resitance
Ref. Current
Ref. Voltage ➀
Offset Voltage
Self Bias I ➀ ➁
Self Bias II ➀ ➂
VRT to VRB
VRT
VRB
VRT
VRB
VRBS
VRTS-VRBS
VRTS
230
4.5
+1.8
0
–10
0
+0.6
+1.96
+2.25
300
6.6
—
—
–35
+15
+0.64
+2.09
+2.39
450
Ω
8.7
mA
+2.8 Volts
VRT
Volts
–60
mV
+45
mV
+0.68 Volts
+2.21 Volts
+2.53 Volts
DIGITAL INPUTS
Input Voltage (CMOS)
Logic Levels (VIH) "1"
+4
—
—
Volts
Logic Level (VIL) "0"
—
—
+1
Volts
Input Current (@VIH=+DVS)"1"
—
—
5
µA
(@VIL=0) "0"
—
—
5
µA
Clock Pulse Width TPW1
25
—
—
ns
(A/D CLK) TPW0
25
—
—
ns
DIGITAL Outputs
Output Data
Output Voltage
Output Current ➃
Logic Level "1"
Logic Level "0"
Output Current ➄
Logic Level "1"
Logic Level "0"
Output Data Delay, Td
8-bit Binary Parallel
3-State TTL compatible
–1.1
—
+3.7
—
—
mA
—
mA
—
—
16
µA
—
—
16
µA
—
18
30
ns
PERFORMANCE
Resolution
Maximum Sampling Rate
Minimum Sampling Rate
Aperature Delay, TA
Aperature Jitter
Differential Linearity Error
Integral Linearity Error
Differential Gain Error ➅
Differential Phase Error ➅
8
—
—
Bit
20
—
—
MHz
—
—
0.5 MHz
—
4
—
ns
—
30
—
ps
—
±0.3
±0.5 LSB
—
+0.5
+1.3 LSB
—
1
—
%
—
0.5
—
deg
Footnotes:
➀ See Technical Note 4
➁ Short VRB (pin 23) to VRBS (pin 22).
Short VRT (pin 17) to VRTS (pin 16).
➂ Short VRB (pin 23) to A GND.
Short VRT (pin 17) to VRTS (pin 16).
➃ OE=OV, VOH=+DVS–0.5V,
VOL=+0.4V
➄ OE=+DVS, VOH=+DVS, VOL=0V
➅ NTSC 40IRE mode ramp, 14.3MHz
sampling
POWER REQUIREMENTS
Min.
Typ.
Max.
Units
Power Supply (+AVS, +DVS)
I A GND - D GND I
Power Supply Current
Power Dissipation
+4.75
+5.0
+5.25
Volts
—
—
100
mV
—
12
17
mA
—
60
85
mW
Physical/Environmental
Operating Temp. Range
Storage Temp. Range
Package Type
ADC-305-1
ADC-305-3
Weight
ADC-305-1
ADC-305-3
–40 to +85°C
–55 to +150°C
24-pin Plastic DIP
24-pin Plastic SOP
2.0 grams
0.3 grams
Technical Notes
1. The ADC-305 has separate +AVS and +DVS pins. It is recommended that both +AVS
and +DVS be powered from a single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits must be powered from a separate
digital supply. +DVS (pins 11 and 13) and +AVs (pins 14, 15 and 18) should be tied together
externally. DGND (pins 2 and 24) and AGND (pins 20 and 21) should also be tied together
externally. Power supply grounds must be connected at one point to the ground plane directly
beneath the device. Digital returns should not flow through analog grounds.
2. Bypass all power lines to ground with a 0.1µF ceramic chip capacitor in parallel with a 47µF
electrolytic capacitor. Locate the bypass capacitor as close to the unit as possible.
3. Even though the analog input capacitance is a low 15pF, it is recommended that high
frequency input be provided via a high speed buffer amplifier. A parasitic oscillation may be
generated when a high speed amplifier is used. A 75 ohm resister inserted between the output
of an amplifier and the analog input of the ADC-305 will improve the situation. A resistor larger
than 100 ohms may degrade linearity.
4. The input voltage range is determined by voltages applied to VRB (Reference Bottom) and
VRT (Reference Top). Keep to the following equations:
0V≤VRB≤VRT≤2.8V
1.8V≤VRT–VRB≤2.8V
The analog input range is normally 2Vp-p.
Self Bias Mode
a. Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog input range in this case is
+0.64V to +2.73V nominal.
b. Tie VRB to AGND, and tie VRT to VRTS respectively. The analog input voltage range is 0 to
+2.39V in this case. These values may differ from one device to another. Voltage changes on
the +5V supply have a direct influence on the performance of the device. The use of external
references is recommended for applications sensitive to gain error.
External Reference Mode
Tie VRB to AGND, and apply +2V to VRT to use at 0 to +2V input voltage range. The reference
resistance between VRB and VRT is about 300 ohms. It is important to make the output
impedance of the reference source small enough while, at the same time, keeping sufficient
drive capacity. Insert a 0.1µF bypass ceramic chip capacitor between VRT and GND to
minimize the effect of the 20MHz clock running nearby. See Figure 5.
5. Logic inputs are CMOS compatible. Normally a series 74HC is used as a driver. It is
recommended to pull up to +5V if the device is driven with TTL.
6. The start convert (A/D CLK) pulse can be a 50% duty cycle clock. Both TPW1 and TPW0 are
25ns minimum. A slightly longer TPW1 will improve linearity of the system for higher frequency
input signals.
7. The digital data outputs are 3-state and TTL compatible. To enable the 3-state
outputs, connect the OUTPUT ENABLE (pin 1) to GND. To disable, connect it to
+5V. It is recommended that the data outputs be latched and buffered through
output registers.
8. Maximum 30ns (18ns typical) after the rising edge of the Nth conversion pulse, the
result of the (N-3) conversion can be obtained. Data is stored firmly in an output
register, such as an 74LS574, using the rising edge of a start convert pulse as a
trigger. The (N–4) data is stored in this case. See the timing diagrams, Figure 2
and 4.
9. The 20MHz sampling rate is guaranteed. It is not recommended to use this device
at sampling rates slower than 500kHz because the droop characteristics of the
internal sample and holds will then exceed the limit required to maintain the
specified accuracy of the device.
www.murata-ps.com
Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
MDA_ADC-305.B01 Page 2 of 6
Share Link: 
