ADC101S051CISDX View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
ADC101S051CISDX
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'ADC101S051CISDX' PDF : 16 Pages View PDF
Applications Information (Continued)
3.0 ADC101S051 TRANSFER FUNCTION
The output format of the ADC101S051 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC101S051 is VA/1024.
The ideal transfer characteristic is shown in Figure 5. The
transition from an output code of 00 0000 0000 to a code of
00 0000 0001 is at 1/2 LSB, or a voltage of VA/2048. Other
code transitions occur at steps of one LSB.
5.0 ANALOG INPUTS
An equivalent circuit for the ADC101S051’s input is shown in
Figure 7. Diodes D1 and D2 provide ESD protection for the
analog inputs. At no time should the analog input go beyond
(VA + 300 mV) or (GND − 300 mV), as these ESD diodes will
begin conducting, which could result in erratic operation.
The capacitor C1 in Figure 7 has a typical value of 4 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the track / hold switch, and is typically 500
ohms. Capacitor C2 is the ADC101S051 sampling capacitor
and is typically 26 pF. The ADC101S051 will deliver best
performance when driven by a low-impedance source to
eliminate distortion caused by the charging of the sampling
capacitance. This is especially important when using the
ADC101S051 to sample AC signals. Also important when
sampling dynamic signals is an anti-aliasing filter.
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FIGURE 5. Ideal Transfer Characteristic
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FIGURE 7. Equivalent Input Circuit
4.0 TYPICAL APPLICATION CIRCUIT
A typical application of the ADC101S051 is shown in
Figure 6. Power is provided in this example by the National
Semiconductor LP2950 low-dropout voltage regulator, avail-
able in a variety of fixed and adjustable output voltages. The
power supply pin is bypassed with a capacitor network lo-
cated close to the ADC101S051. Because the reference for
the ADC101S051 is the supply voltage, any noise on the
supply will degrade device noise performance. To keep noise
off the supply, use a dedicated linear regulator for this de-
vice, or provide sufficient decoupling from other circuitry to
keep noise off the ADC101S051 supply pin. Because of the
ADC101S051’s low power requirements, it is also possible to
use a precision reference as a power supply to maximize
performance. The three-wire interface is shown connected to
a microprocessor or DSP.
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FIGURE 6. Typical Application Circuit
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC101S051 digital inputs (SCLK and CS) are not
limited by the same maximum ratings as the analog inputs.
The digital input pins are instead limited to +5.25V with
respect to GND, regardless of VA, the supply voltage. This
allows the ADC101S051 to be interfaced with a wide range
of logic levels, independent of the supply voltage.
7.0 MODES OF OPERATION
The ADC101S051 has two possible modes of operation:
normal mode, and shutdown mode. The ADC101S051 en-
ters normal mode (and a conversion process is begun) when
CS is pulled low. The device will enter shutdown mode if CS
is pulled high before the tenth falling edge of SCLK after CS
is pulled low, or will stay in normal mode if CS remains low.
Once in shutdown mode, the device will stay there until CS is
brought low again. By varying the ratio of time spent in the
normal and shutdown modes, a system may trade-off
throughput for power consumption, with a sample rate as low
as zero.
7.1 Normal Mode
The fastest possible throughput is obtained by leaving the
ADC101S051 in normal mode at all times, so there are no
power-up delays. To keep the device in normal mode con-
tinuously, CS must be kept low until after the 10th falling
edge of SCLK after the start of a conversion (remember that
a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before
the 16th falling edge, the device will remain in normal mode,
but the current conversion will be aborted, and SDATA will
return to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
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