ADE7761A View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADE7761A

Energy Metering IC with On-Chip Fault and Missing Neutral Detection

Analog Devices 

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ADE7761A

Parameter

LOGIC INPUTS5

PGA, SCF, S1, and S0

Input High Voltage, VINH

Input Low Voltage, VINL

Input Current, IIN

Input Capacitance, CIN

LOGIC OUTPUTS5

CF, REVP, and FAULT

Output High Voltage, VOH

Output Low Voltage, VOH

F1 and F2

Output High Voltage, VOH

Output Low Voltage, VOH

POWER SUPPLY

VDD

VDD

Value Unit

2.4

V, min

0.8

V, max

±3

μA, max

10

pF, max

4

V, min

1

V, max

4

V, min

1

V, max

4.75 V, min

5.25 V, max

3

mA, max

Test Conditions/Comments

VDD = 5 V ± 5%

VDD = 5 V ± 5%

Typical 10 nA, VIN = 0 V to VDD

VDD = 5 V ± 5%

VDD = 5 V ± 5%

VDD = 5 V ± 5%, ISOURCE = 10 mA

VDD = 5 V ± 5%, ISINK = 10 mA

For specified performance

5 V − 5%

5 V + 5%

1 See plots in the Typical Performance Characteristics section.

2 See the Terminology section for explanation of specifications.

3 See the Fault Detection section for explanation of fault detection functionality.

4 See the Missing Neutral Detection section for explanation of missing neutral detection functionality.

5 Sample tested during initial release and after any redesign or process change that might affect this parameter.

TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, TMIN to TMAX = −40°C to +85°C. Sample tested during

initial release and after any redesign or process change that might affect this parameter. See Figure 2.

Table 2.

Parameter

t1 1

t2

t3

t41

t5

t6

Value

120

See Table 7

1/2 t2

90

See Table 8

CLKIN/4

Unit

Test Conditions/Comments

ms

F1 and F2 Pulse Width (Logic High).

s

Output Pulse Period. See the Transfer Function section.

s

Time Between F1 Falling Edge and F2 Falling Edge.

ms

CF Pulse Width (Logic High).

s

CF Pulse Period. See the Transfer Function section.

s

Minimum Time Between F1 and F2 Pulse.

1 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.

t1

F1

t6

t2

F2

t3

t4

t5

CF

Figure 2. Timing Diagram for Frequency Outputs

Rev. 0 | Page 4 of 24

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