ADIS16136AMLZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADIS16136AMLZ' PDF : 20 Pages View PDF
Data Sheet
ADIS16136
SYSTEM CONTROLS
The ADIS16136 provides a number of system level controls for
managing its operation using the registers listed in Table 28.
Table 28. System Tool Registers
Register Name Address Description
GPIO_CTRL
0x1A
General-purpose I/O control
MSC_CTRL
0x1C
Self test, calibration, data ready
SLP_CTRL
0x24
Sleep mode control
DIAG_STAT
0x26
Error flags
GLOB_CMD
0x28
Single command functions
LOT_ID1
0x32
Lot Identification Code 1
LOT_ID2
0x34
Lot Identification Code 2
LOT_ID3
0x36
Lot Identification Code 3
PROD_ID
0x38
Product identification
SERIAL_NUM 0x3A
Serial number
GLOBAL COMMANDS
The GLOB_CMD register (see Table 29) provides trigger
bits for several operations. Write 1 to the appropriate bit in
GLOB_CMD to start a function. After the function completes,
the bit restores to 0.
Software Reset
Set GLOB_CMD[7] = 1 (DIN = 0xA880) to reset the operation,
which removes all data, initializes all registers from their flash
settings, and starts data collection. This function provides a
firmware alternative to the RST line (see Table 5, Pin 8).
Table 29. GLOB_CMD Bit Descriptions
Bits Description (Default = 0x0000) Execution Time1
[15:8] Not used
N/A
7
Software reset
70 ms
[6:4] Not used
N/A
3
Flash update
70 ms
2
Not used
N/A
1
Factory calibration restore
71 ms
0
Automatic bias correction
N/A2
1 N/A in this column means not applicable.
2 Execution time is based on SMPL_PRD and DEC_RATE settings. This starts
at the next data ready pulse, restarts the decimation cycle, and then writes
to the flash (70 ms) after completing a decimation cycle. With respect to
Figure 18, the decimation cycle time = ND ÷ fS.
MEMORY MANAGEMENT
The data retention of the flash memory depends on the temper-
ature, as shown in Figure 20. The FLASH_CNT register (see
Table 30) provides a 16-bit counter that helps track the number
of write cycles to the nonvolatile flash memory, which helps the
user manage against the endurance rating. The flash updates
every time any of the following bits are set to 1: GLOB_CMD[3],
GLOB_CMD[1], and GLOB_ CMD[0].
Table 30. FLASH_CNT Bit Descriptions
Bits
Description)
[15:0] Binary counter; number of flash updates
600
450
300
150
0
30
40
55
70
85 100 125 135 150
JUNCTION TEMPERATURE (°C)
Figure 20. Flash Memory Retention
Checksum Test
Set MSC_CTRL[11] = 1 (DIN = 0x9D08) to perform a checksum
verification of the internal program memory. This takes a summa-
tion of the internal program memory and compares it with the
original summation value for the same locations (from factory
configuration). Check the results in the DIAG_STAT register
(see Table 34). DIAG_STAT[6] = 0 if the sum matches the
correct value and 1 if it does not. Make sure that the power
supply is within specification for the entire 21 ms that this
function takes to complete.
GENERAL-PURPOSE INPUT/OUTPUT
There are four general-purpose I/O lines, DIO1, DIO2, DIO3,
and DIO4/CLKIN that provide a number of useful functions. The
MSC_CTRL[2:0] bits (see Table 31) control the data ready configu-
ration and have the highest priority for setting either DIO1 or DIO2
(but not both). The ALM_CTRL[2:0] control bits (see Table 26)
provide the alarm indicator configuration control and have the
second highest priority for DIO1 or DIO2. When DIO1 and DIO2
are not in use as either data ready or alarm indicator signals, the
GPIO_CTRL register (see Table 32) provides the control and data
bits for them, together with the DIO3 and DIO4 lines.
Data Ready Input/Output Indicator
The factory default setting for MSC_CTRL[2:0] is 110, which
configures DIO1 as a positive data ready indicator signal. A
common option for this function is MSC_CTRL[2:0] = 100
(DIN = 0x9C04), which changes data ready to a negative
polarity for processors that provide only negative triggered
interrupt pins. The pulse width is between 100 μs and 200 μs
over all conditions.
Example Input/Output Configuration
For example, set GPIO_CTRL[7:0] = 0x02 (DIN = 0x9A02)
to set DIO1 as an input and DIO2 as an output. Then, set
GPIO_CTRL[15:8] = 0x02 (DIN = 0x9B02) to set DIO2 in a
high output state. Monitor DIO1 by reading GPIO_CTRL[8]
(DIN = 0x1B00).
Rev. A | Page 15 of 20
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